PIC18F2410-I/SP Microchip Technology, PIC18F2410-I/SP Datasheet - Page 68

• Manufacturer Part Number: PIC18F2410-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2410-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2X1X/4X1X
TABLE 5-2:
DS39636A-page 66
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Bytes
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
ECCPASE
VDIRMAG
TMR0ON
ABDOVF
P1M1
CVREN
PRSEN
C2OUT
WCOL
IDLEN
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED)
(2)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ECCPAS2
ACKSTAT
T3CCP2
PDC6
P1M0
CVROE
T08BIT
T1RUN
SSPOV
C1OUT
RCIDL
IRCF2
Bit 6
CKE
—
—
—
—
—
—
(2)
(2)
(1)
2
C Slave Mode. SSP Baud Rate Reload Register in I
T1CKPS1
ECCPAS1
T3CKPS1
PDC5
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
DC2B1
IRVST
C2INV
IRCF1
CVRR
T0CS
CHS3
Bit 5
D/A
—
—
—
(2)
ECCPAS0
T1CKPS0
T3CKPS0
HLVDEN
PDC4
ACKEN
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
IRCF0
C1INV
CHS2
SCKP
T0SE
Bit 4
CKP
—
RI
P
Preliminary
(2)
T1OSCEN
CCP1M3
CCP2M3
PSSAC1
T3CCP1
HLVDL3
PDC3
SSPM3
PCFG3
ACQT0
BRG16
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
S
(2)
TMR2ON
CCP1M2
CCP2M2
PSSAC0
T1SYNC
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
PEN
CM2
R/W
PD
—
—
(2)
2
C Master Mode.
‘
0
’
GO/DONE
PSSBD1
. Reset values are shown for 40/44-pin devices;
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
CCP2M1
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
WUE
Bit 1
POR
CM1
UA
—
(2)
(2)
 2004 Microchip Technology Inc.
PSSBD0
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CCP1M0
CCP2M0
HLVDL0
PDC0
SSPM0
PCFG0
ADCS0
ABDEN
T0PS0
ADON
CVR0
SCS0
Bit 0
BOR
SEN
CM0
‘
BF
0
’
. See Section 2.6.4 “PLL in
(2)
(2)
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
0q-1 11q0 42, 48, 92
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
Value on
‘
0
’
. This bit is
on page:
50, 159,
50, 152,
50, 153,
51, 129,
50, 231
50, 247
50, 121
50, 121
50, 124
50, 124
50, 123
50, 160
50, 163
51, 220
51, 220
51, 212
51, 213
51, 130
51, 130
51, 130
51, 130
51, 129
51, 194
51, 146
51, 147
51, 227
51, 221
51, 127
51, 127
51, 125
Details
50, 115
50, 115
50, 113
50, 117
51, 211
30, 50
160
161
162
137