PIC18F2410-I/SP Microchip Technology, PIC18F2410-I/SP Datasheet - Page 375

• Manufacturer Part Number: PIC18F2410-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2410-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

 2004 Microchip Technology Inc.
CLKO and I/O .......................................................... 335
Clock Synchronization ............................................. 171
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 340
Example SPI Master Mode (CKE = 1) ..................... 341
Example SPI Slave Mode (CKE = 0) ....................... 342
Example SPI Slave Mode (CKE = 1) ....................... 343
External Clock (All Modes except PLL) .................... 333
Fail-Safe Clock Monitor ............................................ 250
First Start Bit Timing ................................................ 179
Full-Bridge PWM Output .......................................... 143
Half-Bridge PWM Output ......................................... 142
High/Low-Voltage Detect Characteristics ................ 330
High-Voltage Detect (VDIRMAG = 1) ...................... 234
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 233
Master SSP I
Master SSP I
Parallel Slave Port
Parallel Slave Port (PSP) Read ............................... 111
Parallel Slave Port (PSP) Write ............................... 111
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 145
PWM Direction Change at Near
PWM Output ............................................................ 134
Repeat Start Condition ............................................. 180
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 205
Slave Synchronization ............................................. 157
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 156
SPI Mode (Slave Mode, CKE = 0) ........................... 158
SPI Mode (Slave Mode, CKE = 1) ........................... 158
Synchronous Reception
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 344
C Bus Start/Stop Bits ............................................. 344
C Master Mode (7 or
C Master Mode (7-Bit Reception) .......................... 183
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Transmission) ..................... 169
C Slave Mode (7-Bit Reception,
C Slave Mode (7-Bit Reception,
C Slave Mode (7-Bit Transmission) ....................... 167
C Slave Mode General Call Address
C Stop Condition Receive or
10-Bit Transmission) ........................................ 182
SEN = 0) .......................................................... 168
SEN = 1) .......................................................... 173
SEN = 0) .......................................................... 166
SEN = 1) .......................................................... 172
Sequence (7 or 10-Bit Address Mode) ............ 174
Transmit Mode ................................................. 184
(PIC18F4410/4510/4515/4610) ....................... 339
Auto-Restart Disabled) .................................... 148
Auto-Restart Enabled) ..................................... 148
100% Duty Cycle ............................................. 145
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 336
V
(Master Mode, SREN) ..................................... 208
DD
Rise > T
2
2
C Bus Data ........................................ 346
C Bus Start/Stop Bits ........................ 346
PWRT
) ............................................ 47
DD
,
Preliminary
Timing Diagrams and Specifications ............................... 333
Synchronous Transmission ..................................... 206
Synchronous Transmission
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 337
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
USART Synchronous Transmission
A/D Conversion Requirements ................................ 350
Capture/Compare/PWM (CCP)
CLKO and I/O Requirements ................................... 335
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 333
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 334
Reset, Watchdog Timer,
Timer0 and Timer1 External
USART Synchronous
USART Synchronous
2
C Bus Data Requirements
PIC18F2X1X/4X1X
(Through TXEN) .............................................. 207
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 248
Run Mode .......................................................... 38
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
(Master/Slave) ................................................. 348
(Master/Slave) ................................................. 348
Requirements .................................................. 338
(Master Mode, CKE = 0) .................................. 340
(Master Mode, CKE = 1) .................................. 341
(Slave Mode, CKE = 0) .................................... 342
(Slave Mode, CKE = 1) .................................... 343
(Slave Mode) ................................................... 345
Requirements .................................................. 346
(PIC18F4410/4510/4515/4610) ....................... 339
Oscillator Start-up Timer,
Power-up Timer and
Brown-out Reset Requirements ...................... 336
Clock Requirements ........................................ 337
Receive Requirements .................................... 348
Transmission Requirements ............................ 348
2
2
C Bus Data Requirements ................ 347
C Bus Start/Stop Bits
DD
, V
DD
DD
DD
, Case 1) ...................... 46
, Case 2) ...................... 46
Rise < T
DD
) ............................ 47
DS39636A-page 373
PWRT
) ........... 46