PIC18F47J13-I/PT Microchip Technology, PIC18F47J13-I/PT Datasheet - Page 349

• Manufacturer Part Number: PIC18F47J13-I/PT
• Description: IC PIC MCU 128KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F47J13-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 13 Channel
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: TQFP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.1
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, the
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) bits
also control the baud rate. In Synchronous mode, BRGH
is ignored.
Table 21-1 provides the formula for computation of the
baud rate for different EUSART modes, which only apply
in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 21-1. From
this, the error in baud rate can be determined. An
example calculation is provided in Example 21-1.
Typical baud rates and error values for the various
Asynchronous modes are provided in Table 21-2. It
may be advantageous to use the high baud rate
(BRGH = 1) or the 16-bit BRG to reduce the baud rate
error, or achieve a slow baud rate for a fast oscillator
frequency.
TABLE 21-1:
 2010 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair
SYNC
0
0
0
0
1
1
Baud Rate Generator (BRG)
Configuration Bits
BAUD RATE FORMULAS
BRG16
0
0
1
1
0
1
BRGH
0
1
0
1
x
x
OSC
, the nearest
Preliminary
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
16-bit/Synchronous
8-bit/Asynchronous
8-bit/Asynchronous
8-bit/Synchronous
PIC18F47J13 FAMILY
Writing a new value to the SPBRGHx:SPBRGx
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer
overflow before outputting the new baud rate.
When
SPBRGH:SPBRG values of 0000h and 0001h are not
supported. In the Asynchronous mode, all BRG values
may be used.
21.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
21.1.2
The data on the RXx pin (either RC7/CCP10/PMA4/
RX1/DT1/RP18 or RPn/RX2/DT2) is sampled three
times by a majority detect circuit to determine if a high or
a low level is present at the RXx pin.
operated
OPERATION IN POWER-MANAGED
MODES
SAMPLING
in
the
Baud Rate Formula
F
F
F
OSC
OSC
OSC
Synchronous
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39974A-page 349
mode,