PIC18F47J13-I/PT Microchip Technology, PIC18F47J13-I/PT Datasheet
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PIC18F47J13-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F47J13 Family Data Sheet 28/44-Pin, High-Performance Microcontrollers with nanoWatt XLP Technology Preliminary DS39974A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F47J13 Family 28/44-Pin, High-Performance Microcontrollers with nanoWatt XLP Technology Power Management Features with nanoWatt XLP for Extreme Low Power: • Deep Sleep mode: CPU Off, Peripherals Off, SRAM Off, Currents Down and 700 nA with RTCC: - Able to wake-up on external triggers, programmable WDT ...
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... PIC18F47J13 FAMILY PIC18F Device PIC18F26J13 28 64K 3760 19 PIC18F27J13 28 128K 3760 19 PIC18F46J13 44 64K 3760 25 PIC18F47J13 44 128K 3760 25 PIC18LF26J13 28 64K 3760 19 PIC18LF27J13 28 128K 3760 19 PIC18LF46J13 44 64K 3760 25 PIC18LF47J13 44 128K 3760 25 DS39974A-page 4 MSSP 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 Preliminary 2010 Microchip Technology Inc. ...
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... Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY ...
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... PIC18F47J13 FAMILY Pin Diagrams (Continued) 44-Pin QFN RC7/CCP10/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 RB0/AN12/C3IND/INT0/RP3 RB1/AN10/C3INC/PMBE/RTCC/RP4 RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5 RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin Legend: Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “ ...
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... Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”. For the QFN package recommended that the bottom pad be connected to V Note: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 28 1 RB7/CCP7/KBI3/PGD/RP10 MCLR ...
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... Instruction Set Summary .......................................................................................................................................................... 433 29.0 Development Support............................................................................................................................................................... 483 30.0 Electrical Characteristics .......................................................................................................................................................... 487 31.0 Packaging Information.............................................................................................................................................................. 529 Appendix A: Revision History............................................................................................................................................................. 541 Appendix B: Migration From PIC18F46J11 to PIC18F47J13............................................................................................................. 541 The Microchip Web Site ..................................................................................................................................................................... 555 Customer Change Notification Service .............................................................................................................................................. 555 Customer Support .............................................................................................................................................................................. 555 Reader Response .............................................................................................................................................................................. 556 Product Identification System ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Preliminary DS39974A-page 9 ...
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... PIC18F47J13 FAMILY NOTES: DS39974A-page 10 Preliminary 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F47J13 FAMILY 1.1.2 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F47J13 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... Section 30.0 “Electrical Characteristics” for time-out periods. 1.3 Details on Individual Family Devices Devices in the PIC18F47J13 family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: • ...
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... Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10/12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F47J13 FAMILY PIC18F26J13 DC – 48 MHz 64 32,768 3.8 30 Ports ECCP and 7 CCP MSSP (2), Enhanced USART (2) ...
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... PIC18F47J13 FAMILY FIGURE 1-1: PIC18F2XJ13 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 Address Latch Program Memory Data Latch Instruction Bus <16> Timing OSC2/CLKO Generation OSC1/CLKI 8 MHz INTOSC INTRC Oscillator Precision Band Gap Reference Voltage Regulator V /V DDCORE CAP ADC RTCC HLVD ...
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... CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 Note 1: See Table 1-3 for I/O port pin descriptions. 2: The on-chip voltage regulator is always enabled by default. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) ...
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... PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC (2) MCLR 1 OSC1/CLKI/RA7 9 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 10 OSC2 CLKO (1) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. ...
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... Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. 27 I/O TTL/DIG Digital I/O ...
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... PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RB0/AN12/C3IND/INT0/RP3 21 RB0 AN12 C3IND INT0 RP3 RB1/AN10/C3INC/RTCC/RP4 22 RB1 AN10 C3INC RTCC RP4 RB2/AN8/C2INC/CTED1/ 23 REFO/RP5 RB2 AN8 C2INC CTED1 REFO RP5 RB3/AN9/C3INA/CTED2/ 24 RP6 RB3 AN9 C3INA ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) (2) 22 I/O TTL/DIG Digital I/O ...
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... PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RC0/T1OSO/T1CKI/RP11 11 RC0 T1OSO T1CKI RP11 RC1/CCP8/T1OSI/RP12 12 RC1 CCP8 T1OSI RP12 RC2/AN11/C2IND/CTPLS/RP13 13 RC2 AN11 C2IND CTPLS RP13 RC3/SCK1/SCL1/RP14 14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 15 RC4 SDI1 SDA1 ...
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... Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN 5 P — Ground reference for logic and I/O pins. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: DS39974A-page 22 Pin Buffer 44- ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: DS39974A-page 24 Pin Buffer 44- ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: DS39974A-page 26 Pin Buffer 44- ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: DS39974A-page 28 Pin Buffer 44- ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer ...
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... PIC18F47J13 FAMILY NOTES: DS39974A-page 30 Preliminary 2010 Microchip Technology Inc. ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F47J13 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC18F47J13 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...
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... PIC18F47J13 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... Phase Locked Loop (PLL). Its use is described in Section 3.2.5.1 “OSCTUNE Register”. 3.2 Oscillator Types PIC18F47J13 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table 3-1. For oscillator modes which ...
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... PIC18F47J13 FAMILY FIGURE 3-1: PIC18F47J13 FAMILY CLOCK DIAGRAM Primary Oscillator FOSC<2> OSC2 OSC1 0 1 FOSC<2> PLLSEL CFGPLLEN 1 (2) 4x PLL 0 Secondary Oscillator T1OSO T1OSI Internal Oscillator Block 8 MHz 8 MHz INTRC 31 kHz The 96 MHz PLL requires a 4 MHz input and it produces a 96 MHz output. The 96 MHz PLL prescaler enables Note 1: source clocks 12, 16, 20, 24 MHz to provide the 4 MHz input ...
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... See the notes following Table 3-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz 2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 3-3: Osc Type HS the crystal Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... PLL circuit will be used by the application. 3.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F47J13 family devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. The internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins ...
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... INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency ...
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... PIC18F47J13 FAMILY REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh) R/W-0 R/W-0 R/W-0 (1) INTSRC PLLEN TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) ...
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... Switching Like previous PIC18 enhanced PIC18F47J13 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F47J13 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available ...
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... DS39974A-page 42 3.3.2 OSCILLATOR TRANSITIONS PIC18F47J13 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. Note 1: Default output frequency of INTOSC on Reset (4 MHz). 2: When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no 3: effect. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY (2) R/W-1 R/W-0 R/W-1 (3) SOSCDRV SOSCGO — ...
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... PIC18F47J13 FAMILY 3.4 Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F47J13 family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
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... MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current consumption Section 30.2 “DC Characteristics: Power-Down and Supply Current PIC18F47J13 Family (Industrial)”. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.6 Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applica- tions ...
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... PIC18F47J13 FAMILY NOTES: DS39974A-page 46 Preliminary 2010 Microchip Technology Inc. ...
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... LOW-POWER MODES The PIC18F47J13 family devices can manage power consumption through clocking to the CPU and the peripherals. In general, reducing the clock frequency and number of circuits being clocked reduces power consumption. For managing power in an application, the primary modes of operation are: • ...
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... PIC18F47J13 FAMILY TABLE 4-1: LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> Mode (1) (1) DSEN IDLEN SCS<1:0> Sleep 0 0 Deep 1 0 (3) Sleep PRI_RUN N/A 0 SEC_RUN N/A 0 RC_RUN N/A 0 PRI_IDLE 0 1 SEC_IDLE 0 1 RC_IDLE 0 1 IDLEN and DSEN reflect their values when the SLEEP instruction is executed. ...
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... Note 1024 OST OSC 2010 Microchip Technology Inc. PIC18F47J13 FAMILY The Timer1 oscillator should already be Note: running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the ...
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... PIC18F47J13 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times ...
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... T OST OSC PLL 2010 Microchip Technology Inc. PIC18F47J13 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 27 ...
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... PIC18F47J13 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS< ...
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... TRANSITION TIMING FOR ENTRY TO IDLE MODE OSC1 CPU Clock Peripheral Clock Program PC Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F47J13 FAMILY CSD PC Preliminary DS39974A-page 53 ...
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... PIC18F47J13 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP ...
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... Executing the SLEEP instruction immediately after setting DSEN and the single NOP (no interrupts in between) 2010 Microchip Technology Inc. PIC18F47J13 FAMILY In order to minimize the possibility of inadvertently enter- ing Deep Sleep, the DSEN bit is cleared in hardware two instruction cycles after having been set. Therefore, ...
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... PIC18F47J13 FAMILY 4.6.2 I/O PINS DURING DEEP SLEEP During Deep Sleep, the general purpose I/O pins will retain their previous states. Pins that are configured as inputs (TRISx bit set) prior to entry into Deep Sleep will remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRISx bit clear) prior to entry into Deep Sleep will remain as output pins during Deep Sleep ...
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... Deep Sleep bit, DS (WDTCON<3>). This bit will be set if there was an exit from Deep Sleep mode. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 14. Clear the Deep Sleep bit, DS (WDTCON<3>). 15. Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers. 16. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCONL< ...
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... PIC18F47J13 FAMILY 4.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are Register 4-1 through Register 4-6. REGISTER 4-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) R/W-0 U-0 U-0 (1) DSEN — — bit Reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
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... DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep 2010 Microchip Technology Inc. PIC18F47J13 FAMILY (1) R/W-xxxx U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared drops below the normal BOR threshold outside of Deep ...
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... PIC18F47J13 FAMILY REGISTER 4-6: DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) R/W-0 U-0 R/W-0 DSFLT — DSULP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 DSFLT: Deep Sleep Fault Detected bit Deep Sleep Fault was detected during Deep Sleep ...
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... Configure Sleep mode. 8. Enter Sleep mode. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY When the voltage on RA0 drops below V will be generated, which will cause the device to wake-up and execute the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. ...
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... PIC18F47J13 FAMILY EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for < 10000; i++) Nop(); ...
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... Write 55h to EECON2. 2. Write 0AAh to EECON2. 3. Immediately write the modified RTCCMD setting to PMDIS1. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.8 Peripheral Module Disable All peripheral modules (except for I/O ports) also have a second control bit that can disable their functionality. ...
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... PIC18F47J13 FAMILY NOTES: DS39974A-page 64 Preliminary 2010 Microchip Technology Inc. ...
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... RESET The PIC18F47J13 family of devices differentiates among various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset ...
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... PIC18F47J13 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...
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... POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 5.4 Brown-out Reset (BOR) The “F” devices in the PIC18F47J13 family incorporate two types of BOR circuits: one which monitors V and one which monitors V DDCORE DD circuit can be active at a time ...
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... Electrostatic always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F47J13 family devices is a counter which uses the INTRC source as the clock input. While the PWRT is counting, the device is held in Reset. ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F47J13 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ): CASE 1 ...
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... PIC18F47J13 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...
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... PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F2XJ13 PIC18F4XJ13 POSTINC2 PIC18F2XJ13 PIC18F4XJ13 POSTDEC2 PIC18F2XJ13 PIC18F4XJ13 PREINC2 PIC18F2XJ13 PIC18F4XJ13 PLUSW2 PIC18F2XJ13 PIC18F4XJ13 FSR2H PIC18F2XJ13 PIC18F4XJ13 FSR2L PIC18F2XJ13 PIC18F4XJ13 STATUS PIC18F2XJ13 PIC18F4XJ13 TMR0H PIC18F2XJ13 PIC18F4XJ13 TMR0L ...
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... See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...
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... PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR1 PIC18F2XJ13 PIC18F4XJ13 PIR1 PIC18F2XJ13 PIC18F4XJ13 PIE1 PIC18F2XJ13 PIC18F4XJ13 RCSTA2 PIC18F2XJ13 PIC18F4XJ13 OSCTUNE PIC18F2XJ13 PIC18F4XJ13 T1GCON PIC18F2XJ13 PIC18F4XJ13 T3GCON PIC18F2XJ13 PIC18F4XJ13 (5) TRISE — PIC18F4XJ13 (5) TRISD — PIC18F4XJ13 TRISC ...
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... See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...
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... PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMDOUT2L — PIC18F4XJ13 PMDIN2H — PIC18F4XJ13 — PMDIN2L PIC18F4XJ13 PMEH — PIC18F4XJ13 PMEL — PIC18F4XJ13 PMSTATH — PIC18F4XJ13 PMSTATL — PIC18F4XJ13 CVRCON PIC18F2XJ13 PIC18F4XJ13 CCPTMRS0 PIC18F2XJ13 PIC18F4XJ13 CCPTMRS1 ...
Page 77
... See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...
Page 78
... PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices CCPR9H PIC18F2XJ13 PIC18F4XJ13 CCPR9L PIC18F2XJ13 PIC18F4XJ13 CCP9CON PIC18F2XJ13 PIC18F4XJ13 CCPR10H PIC18F2XJ13 PIC18F4XJ13 CCPR10L PIC18F2XJ13 PIC18F4XJ13 CCP10CON PIC18F2XJ13 PIC18F4XJ13 RPINR24 PIC18F2XJ13 PIC18F4XJ13 RPINR23 PIC18F2XJ13 PIC18F4XJ13 RPINR22 PIC18F2XJ13 PIC18F4XJ13 RPINR21 ...
Page 79
... See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...
Page 80
... PIC18F47J13 FAMILY NOTES: DS39974A-page 80 Preliminary 2010 Microchip Technology Inc. ...
Page 81
... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all ‘0’s (a NOP instruction). The PIC18F47J13 family offers a range of on-chip Flash program memory sizes, from 64 Kbytes (up to 32,768 single-word (65,536 single-word instructions). ...
Page 82
... CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 6-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F47J13 family. Figure 6-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 27.1 “ ...
Page 83
... Microchip Technology Inc. PIC18F47J13 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...
Page 84
... PIC18F47J13 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack ...
Page 85
... RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 86
... PIC18F47J13 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
Page 87
... ADDWF 2010 Microchip Technology Inc. PIC18F47J13 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 88
... The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F47J13 family implements all available banks and provides 3.8 Kbytes of data memory available to the user. Figure 6-6 provides the data memory organization for the devices ...
Page 89
... FIGURE 6-6: DATA MEMORY MAP FOR PIC18F47J13 FAMILY DEVICES BSR3:BSR0 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
Page 90
... PIC18F47J13 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to Note 1: the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 91
... PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. Reserved; do not write to this location. 5: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. ...
Page 92
... PIC18F47J13 FAMILY TABLE 6-3: NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address Name Address Name F5Fh PMCONH F3Fh RTCCFG F5Eh PMCONL F3Eh RTCCAL F5Dh PMMODEH F3Dh REFOCON F5Ch PMMODEL F3Ch PADCFG1 F5Bh PMDOUT2H F3Bh RTCVALH F5Ah PMDOUT2L F3Ah RTCVALL F59h PMDIN2H F39h — ...
Page 93
... PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: 2010 Microchip Technology Inc. ...
Page 94
... EUSART1 Receive Register FAEh TXREG1 EUSART1 Transmit Register FADh TXSTA1 CSRC TX9 Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 94 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
Page 95
... EUSART1 Baud Rate Generator High Byte F7Eh BAUDCON1 ABDOVF RCIDL Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Bit 5 Bit 4 ...
Page 96
... Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) F4Dh DSCONH DSEN — F4Ch DSCONL — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 96 Bit 5 Bit 4 Bit 3 Bit 2 RXDTP TXCKP BRG16 — ...
Page 97
... CCP7CON — — F08h CCPR8H Capture/Compare/PWM Register 8 High Byte Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Bit 5 Bit 4 Bit 3 — ...
Page 98
... ED8h RPOR24 — — (2) ED7h RPOR23 — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 98 Bit 5 Bit 4 Bit 3 Bit 2 DC8B1 DC8B0 CCP8M3 CCP8M2 DC9B1 ...
Page 99
... EB1h — — — EB0h — — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 100
... PIC18F47J13 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
Page 101
... LSB. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 “General Purpose 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. ...
Page 102
... PIC18F47J13 FAMILY 6.4.3.1 FSR Registers and the INDF Operand (INDF) At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value ...
Page 103
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations ...
Page 104
... PIC18F47J13 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space ...
Page 105
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
Page 106
... PIC18F47J13 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
Page 107
... Program Memory (TBLPTR) The Table Pointer register points to a byte in program memory. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 108
... PIC18F47J13 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) The Table Pointer actually points to one of 64 holding registers, the address of which is determined by Note 1: TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “ ...
Page 109
... The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 110
... PIC18F47J13 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TABLE POINTER REGISTER ...
Page 111
... MOVF TABLAT, W MOVWF WORD_ODD 2010 Microchip Technology Inc. PIC18F47J13 FAMILY The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 112
... PIC18F47J13 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
Page 113
... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC the PIC18F47J13 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...
Page 114
... PIC18F47J13 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 0x55 MOVWF EECON2 MOVLW 0xAA MOVWF EECON2 BSF EECON1, WR BSF ...
Page 115
... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING) The PIC18F47J13 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1 ...
Page 116
... PIC18F47J13 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.4 UNEXPECTED TERMINATION OF ...
Page 117
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F47J13 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: ...
Page 118
... PIC18F47J13 FAMILY Example 8-3 provides the instruction sequence for unsigned multiplication. Equation 8-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L 16 = (ARG1H · ARG2H · (ARG1H · ARG2L · 2 ...
Page 119
... INTERRUPTS Devices of the PIC18F47J13 family have multiple inter- rupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 120
... PIC18F47J13 FAMILY FIGURE 9-1: PIC18F47J13 FAMILY INTERRUPT LOGIC PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<5:0> PIE5<5:0> IPR5<5:0> PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> PIR4<7:0> PIE4<7:0> IPR4<7:0> ...
Page 121
... A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T Note 1: condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 122
... PIC18F47J13 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 123
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 INT2IE ...
Page 124
... PIC18F47J13 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) ...
Page 125
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 R/W-0 R/W-0 — BCL1IF HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 126
... PIC18F47J13 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) ...
Page 127
... No TMR register capture occurred Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Unused in this mode. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘0’ ...
Page 128
... PIC18F47J13 FAMILY REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 (ACCESS F98h) U-0 U-0 R-0 — — CM3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5 CM3IF: Comparator Interrupt Flag bit ...
Page 129
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt These bits are unimplemented on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ...
Page 130
... PIC18F47J13 FAMILY REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit ...
Page 131
... Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
Page 132
... PIC18F47J13 FAMILY REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh) R/W-0 R/W-0 R/W-0 CCP10IE CCP9IE CCP8IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit ...
Page 133
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority These bits are unimplemented on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 134
... PIC18F47J13 FAMILY REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ...
Page 135
... TMR3GIP: Timer3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CTMUIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 136
... PIC18F47J13 FAMILY REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h) R/W-1 R/W-1 R/W-1 CCP10IP CCP9IP CCP8IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits 1 = High priority 0 = Low priority bit 0 ...
Page 137
... For details on bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
Page 138
... PIC18F47J13 FAMILY 9.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set ...
Page 139
... RD PORT Note 1: I/O pins have diode protection 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 140
... PIC18F47J13 FAMILY 10.1.3 INTERFACING SYSTEM Though the V of the PIC18F47J13 family is 3.6V, DDMAX these devices are still capable of interfacing with 5V systems, even if the V of the target system is above IH 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 10-2), clearing the LAT bit for that ...
Page 141
... ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘0’ ...
Page 142
... PIC18F47J13 FAMILY REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3 CCP10OD: CCP10 Open-Drain Output Enable bit ...
Page 143
... CMxCON registers. To use RAx as digital inputs necessary to turn off the comparators Power-on Reset (POR), RA5 and Note: RA<3:0> are configured as analog inputs and read as ‘0’. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘ ...
Page 144
... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRISx bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13) ...
Page 145
... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRISx bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13) ...
Page 146
... PIC18F47J13 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 147
... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4: 2010 Microchip Technology Inc. ...
Page 148
... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4: DS39974A-page 148 ...
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... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4: TABLE 10-6: ...
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... PIC18F47J13 FAMILY 10.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
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... I C/SMB = I C/SMBus input buffer Don’t care (TRISx bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13). 2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O ...
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... I C/SMB = I C/SMBus input buffer Don’t care (TRISx bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13). TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name ...
Page 153
... All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output POR, these pins are configured as Note: digital inputs. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY EXAMPLE 10-5: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ...
Page 154
... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; I input buffer Don’t care (TRISx bit does not affect port direction or is overridden for this option). Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Note 1: DS39974A-page 154 ...
Page 155
... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; I input buffer Don’t care (TRISx bit does not affect port direction or is overridden for this option). Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Note 1: TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD ...
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... PORTE, TRISE and LATE Registers PORTE is available only in 44-pin devices. Note: Depending on the particular PIC18F47J13 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs ...
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... All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad bit 6 REPU: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad 2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O I/O Type I ST PORTE< ...
Page 158
... I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F47J13 family application that needs to use more than one peripheral, multi- plexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option ...
Page 159
... Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY with one of the pin selectable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral. ...
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... PIC18F47J13 FAMILY 10.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control reg- ister associated with a particular pin dictates the periph- eral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corre- sponds to one of the peripherals and that peripheral’ ...
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... ESD or other external events), a Configuration Mismatch Reset will be triggered. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.7.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be con- figured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CONFIG3H< ...
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... PIC18F47J13 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled com- pletely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output ...
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... PERIPHERAL PIN SELECT REGISTERS The PIC18F47J13 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 10-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EBFh) U-0 U-0 U-0 — ...
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... PIC18F47J13 FAMILY REGISTER 10-8: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE3h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
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... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R<4:0>: Assign Input Capture 3 (ECCP3) to the Corresponding RPn Pin bits 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 IC1R4 IC1R3 IC1R2 U = Unimplemented bit, read as ‘0’ ...
Page 166
... PIC18F47J13 FAMILY REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
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... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 RX2DT2R4 RX2DT2R3 RX2DT2R2 U = Unimplemented bit, read as ‘0’ ...
Page 168
... PIC18F47J13 FAMILY REGISTER 10-20: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFCh) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 169
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 OCFAR4 OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ...
Page 170
... PIC18F47J13 FAMILY REGISTER 10-24: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC1h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 171
... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP3R4 RP3R3 RP3R2 U = Unimplemented bit, read as ‘ ...
Page 172
... PIC18F47J13 FAMILY REGISTER 10-30: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED EC6h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 173
... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 RP9R3 RP9R2 U = Unimplemented bit, read as ‘ ...
Page 174
... PIC18F47J13 FAMILY REGISTER 10-36: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ECCh) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 175
... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP15R4 RP15R3 RP15R2 U = Unimplemented bit, read as ‘ ...
Page 176
... PIC18F47J13 FAMILY REGISTER 10-42: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED2h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 177
... Unimplemented: Read as ‘0’ bit 4-0 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 10-14 for peripheral function numbers) RP23 pins are not available on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 RP21R2 U = Unimplemented bit, read as ‘ ...
Page 178
... PIC18F47J13 FAMILY REGISTER 10-48: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED ED8h) U-0 U-0 U-0 — — — bit 7 R/W = Readable bit, Writable bit if IOLOCK = 0 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ ...
Page 179
... PIC18LF46J13 and PIC18LF47J13. FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Key features of the PMP module are: • bits of Addressing when using Data/Address Multiplexing • Programmable Address Lines • One Chip Select Line • ...
Page 180
... PIC18F47J13 FAMILY 11.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. 11.1.1 ...
Page 181
... Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) This register is only available on 44-pin devices. Note 1: These bits have no effect when their corresponding pins are used as address lines. 2: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY (2) (2) U-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ...
Page 182
... PIC18F47J13 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh) R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 = Port is not busy bit 6-5 IRQM< ...
Page 183
... Wait This register is only available on 44-pin devices. Note 1: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. 2: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...
Page 184
... PIC18F47J13 FAMILY REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h) R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 PTEN<15:14>: PMCS Port Enable bits 1 = PMA<15:14> function as either PMA<15:14> or PMCS 0 = PMA< ...
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... OB<3:0>E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted This register is only available on 44-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 R-0 R-0 — IB3F IB2F U = Unimplemented bit, read as ‘ ...
Page 186
... PIC18F47J13 FAMILY 11.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: • PMDIN1H and PMDIN1L • PMDIN2H and PMDIN2L • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • ...
Page 187
... Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. Note 1: 2010 Microchip Technology Inc. PIC18F47J13 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...
Page 188
... PIC18F47J13 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins. 11.2.1 LEGACY MODE (PSP) ...
Page 189
... PMRD PMD<7:0> IBF OBE PMPIF 2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented on to PMD<7:0>. Figure 11-4 provides the timing for the control signals in Read mode ...
Page 190
... PIC18F47J13 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE PORT MODE Buffered Parallel Slave Port mode is functionally identical to the Legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘ ...
Page 191
... ADDR<1:0>. Table 11-1 provides the corresponding FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF 2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 11-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 PMDOUT1H (1) 01 ...
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... PIC18F47J13 FAMILY 11.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table 11-1 provides the corresponding input registers and their associated address ...
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... PMCONL register. Note that the polarity of control signals that share the 2010 Microchip Technology Inc. PIC18F47J13 FAMILY same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used. ...
Page 194
... PIC18F47J13 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) ...
Page 195
... Then, the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. 2010 Microchip Technology Inc. PIC18F47J13 FAMILY If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two bus reads. The first read data byte is placed into the PMDIN1L register and the second read data byte is placed into the PMDIN1H ...
Page 196
... PIC18F47J13 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS ...
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... Address<7:0> PMD<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY 2010 Microchip Technology Inc. PIC18F47J13 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data Preliminary ...
Page 198
... PIC18F47J13 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: ...
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... PMCS PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY 2010 Microchip Technology Inc. PIC18F47J13 FAMILY LSB MSB LSB MSB LSB MSB Preliminary ...
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... PIC18F47J13 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF ...