PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 408

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
Timing Diagrams and Specifications
DS39635C-page 408
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 376
Transition for Entry to PRI_IDLE Mode ...................... 51
Transition for Entry to SEC_RUN Mode .................... 47
Transition for Entry to Sleep Mode ............................ 50
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 51
Transition for Wake From Sleep (HSPLL) ................. 50
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 49
USART Synchronous Receive (Master/Slave) ........ 386
USART Synchronous Transmission
A/D Conversion Requirements ................................ 388
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 372
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
External Clock Requirements .................................. 370
I
I
2
2
C Bus Data Requirements (Slave Mode) .............. 383
C Bus Start/Stop Bits Requirements
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 292
PRI_RUN Mode ................................................. 49
PRI_RUN Mode (HSPLL) .................................. 47
(Master/Slave) .................................................. 386
Internal RC Accuracy ....................................... 371
(All CCP Modules) ........................................... 377
(Master Mode, CKE = 0) .................................. 378
(Master Mode, CKE = 1) .................................. 379
(Slave Mode, CKE = 0) .................................... 380
Requirements (CKE = 1) .................................. 381
(Slave Mode) .................................................... 382
DD
, V
DD
DD
DD
, Case 1) ....................... 60
, Case 2) ....................... 60
Rise T
PWRT
) .............. 60
Top-of-Stack Access .......................................................... 70
TRISE Register
TSTFSZ ........................................................................... 337
Two-Speed Start-up ................................................. 281, 292
Two-Word Instructions
TXSTA1 Register
TXSTA2 Register
V
Voltage Reference Specifications .................................... 366
W
Watchdog Timer (WDT) ........................................... 281, 290
WCOL ...................................................... 205, 206, 207, 210
WCOL Status Flag ................................... 205, 206, 207, 210
WWW Address ................................................................ 409
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 337
XORWF ........................................................................... 338
Master SSP I
Master SSP I
PLL Clock ................................................................ 371
Program Memory Read Requirements .................... 373
Program Memory Write Requirements .................... 374
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
USART Synchronous Receive Requirements ......... 386
USART Synchronous Transmission
PSPMODE Bit .......................................................... 148
Example Cases .......................................................... 74
BRGH Bit ................................................................. 221
BRGH Bit ................................................................. 244
Associated Registers ............................................... 291
Control Register ....................................................... 290
During Oscillator Failure .......................................... 293
Programming Considerations .................................. 290
Requirements .................................................. 384
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 375
Requirements .................................................. 376
Requirements .................................................. 386
2
2
C Bus Data Requirements ................ 385
C Bus Start/Stop Bits
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