PIC18LF2410-I/SO Microchip Technology, PIC18LF2410-I/SO Datasheet - Page 41
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PIC18LF2410-I/SO
Manufacturer Part Number
PIC18LF2410-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF2410-ISO.pdf
(376 pages)
2.PIC18LF2410-ISO.pdf
(8 pages)
3.PIC18LF2410-ISO.pdf
(16 pages)
4.PIC18LF2410-ISO.pdf
(6 pages)
5.PIC18LF2410-ISO.pdf
(6 pages)
6.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18LF2410-I/SO
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Interface
I2C, SPI, USART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2410-I/SO
Manufacturer:
TOSHIBA
Quantity:
3 000
- PIC18LF2410-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- Current page: 41 of 376
- Download datasheet (7Mb)
4.0
The PIC18F2X1X/4X1X devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 22.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
OSC1
MCLR
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
2: See Table 4-2 for time-out situations.
RESET
Instruction
INTRC
RESET
OST/PWRT
Pointer
32 μs
Stack
( )_IDLE
Brown-out
Time-out
V
(1)
Detect
Sleep
DD
WDT
Reset
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 8.0
Section 4.4 “Brown-out Reset (BOR)”.
PIC18F2X1X/4X1X
RCON Register
“Interrupts”.
S
R
BOR
DS39636D-page 43
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(2)
in
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