DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F3012-30I/P
• Description: IC DSPIC MCU/DSP 24K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F3012-30IP

dsPIC30F3012/3013
13. Module: I/O Port – Port Pin Multiplexed
14. Module: I
15. Module: Timer
16. Module: PLL Lock Status Bit
DS80255F-page 10
If the user application enables the auto-baud
feature in the UART module, the I/O pin
multiplexed with the IC1 (Input Capture) pin cannot
be used as a digital input.
Work around
None.
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are config-
ured for 10-bit addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
When the timer is being operated in Asynchronous
mode using the secondary oscillator (32.768 kHz)
and the device is put into Sleep mode, a clock
switch to any other oscillator mode before putting
the device to Sleep prevents the timer from waking
the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in Asynchronous mode
using the secondary oscillator (32.768 kHz).
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
The user application must include an oscillator
failure trap service routine. In the trap service
routine, first inspect the status of the Clock Failure
Status bit (OSCCON<3>). If this bit is clear, return
from the trap service routine immediately and
continue program execution.
2
C devices, the addresses as well as bits
with IC1
2
C
2
C devices on the bus, one of
17. Module: PSV Operations
18. Module: I
19. Module: I
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
In 10-bit Addressing mode, some address
matches don't set the RBF flag or load the receive
register I2CxRCV, if the lower address byte
matches the reserved addresses. In particular,
these include all addresses with the form
XX0000XXXX
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
mode) with pre/post-decrement
than
2
2
2
C
C
C module is configured as a 10-bit
0x02;
and
© 2008 Microchip Technology Inc.
XX1111XXXX,
however,
the
with
module
the