DSPIC30F3012-30I/SO Microchip Technology, DSPIC30F3012-30I/SO Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F3012-30I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 18SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301230ISO

21. Module: 32 kHz Low-Power (LP)
22. Module: OSC2 Pin
EXAMPLE 10:
© 2010 Microchip Technology Inc.
.include "p30fxxxx.inc"
MOV
MOV
MOV
MOV.b
MOV.b
BSET.b [w1], #6;set poscalar to divide by 4
function when the device is placed in Sleep mode.
The LP oscillator is located on the SOSCO and
SOSCI device pins and serves as a secondary
crystal clock source for low-power operation. The
LP oscillator can also drive Timer1 for a real-time
clock application. The LP oscillator does not
Work around
If the application needs to wake up periodically
from Sleep mode using an internal timer, the
Watchdog Timer may be enabled prior to enter-
ing Sleep mode. When the Watchdog Timer
expires, code execution will resume from the
instruction immediately following the SLEEP
instruction.
Affected Silicon Revisions
When the FRC Clock mode is selected, the OSC2
pin cannot be used for I/O.
Work around
Use the FRC with PLL 4x Clock mode. After the
application powers up, program the Oscillator
Postscaler Selection bits (OSCCON<7:6>) to
‘01’ to divide the clock by 4. The OSCCON is a
write-protected register and an unlock sequence
must be used to modify the Oscillator Postscaler
Selection bits. This work around is shown in
Example 10.
Affected Silicon Revisions
B0
B0
X
X
#OSCCONL, w1;prepare unlock sequence
#0x46, w2
#0x57, w3
w2, [w1];unlock sequence step 1
w3, [w1];unlock sequence step 2
B1
B1
Oscillator
23. Module: OSC2 Pin
24. Module: ADC
The port pin, RC15, is multiplexed with the primary
oscillator pin, OSC2. When pin RC15 is required
for digital input/output, specific bits in the Oscillator
Configuration Fuse register, FOSC, may be set up
as follows:
• FOS<2:0> bits (FOSC<10:8>) configured for
• FPR<4:0> bits (FOSC<4:0>) may be
For this revision of silicon, if the RC15 digital I/O
port function is desired, the FPR<4:0> bits in the
FOSC Configuration Fuse register may not be set
up for FRC w/PLL 4x/8x/16x modes.
Work around
None. In future revisions of silicon, port pin RC15
may also be configured for digital I/O when the
FPR<4:0> bits in the FOSC Configuration Fuse
register are set up for FRC w/PLL 4x/8x/16x
modes.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Affected Silicon Revisions
B0
B0
LP, LPRC, FRC, ECIO, ERCIO or ECIO
w/PLL 4x/8x/16x
configured for ECIO w/PLL 4x/8x/16x
X
X
dsPIC30F3012/3013
B1
B1
X
PD
) may exceed the specifications listed
PD
DS80448D-page 15
specifications
#0