PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 22

• Manufacturer Part Number: PIC18F27J13-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Data Ram Size: 3.76 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 2
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 12 bit
• A/d Channels Available: 10
• Height: 3.43 mm
• Interface Type: I2C, SPI, USART
• Length: 34.4 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.15 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XJXX/4XJXX FAMILY
TABLE 5-5:
DS39687E-page 22
DSWTPS<3:0>
DSWDTEN
DSBOREN
RTCOSC
DSWDTOSC
MSSPMSK
IOL1WAY
WPCFG
WPEND
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
Bit Name
(4)
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
(1,2)
protection, perform an ICSP™ Bulk Erase operation.
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG4L
CONFIG4L
Words
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
Deep Sleep Watchdog Timer Enable bit
1 = DSWDT enabled
0 = DSWDT disabled
Deep Sleep BOR Enable bit
1 = BOR enabled in Deep Sleep
0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
DSWDT Reference Clock Select bit
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<5:0> are write/erase-protected
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
unlock sequence has been completed
WPFP<5:0> settings include the Configuration Words page
WPFP<5:0> settings
DD
Reset; it is reloaded with the programmed value at any device Reset.
Description
© 2009 Microchip Technology Inc.