PIC18F67J11-I/PT Microchip Technology, PIC18F67J11-I/PT Datasheet - Page 4
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J11-I/PT
Manufacturer Part Number
PIC18F67J11-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F66J11-IPT.pdf
(4 pages)
6.PIC18F66J11-IPT.pdf
(4 pages)
7.PIC18F66J11-IPT.pdf
(20 pages)
Specifications of PIC18F67J11-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J11-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F67J11-I/PT
Manufacturer:
MICROCH
Quantity:
20 000
PIC18F87J11 FAMILY
4. Module: SRAM
TABLE 3:
DS80495D-page 4
Voltage Regulator Enabled
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Voltage Regulator Disabled
V
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Note 1:
DDCORE
Any access to SRAM, either in the form of read
or write operations, will increase the current con-
sumption of the device, depending on how often
the SRAM is accessed. A small current increase
is normal, but in this cited silicon revision, the
difference may be significant and of particular
concern for low-power applications.
For further details, see
Work around
None.
Affected Silicon Revisions
A1
2:
3:
X
Condition
Condition
is tied to V
Code execution patterns where no instructions
access SRAM.
Code execution that accesses SRAM, once
every seven instruction cycles.
Code execution where every instruction cycle
executes an instruction that accesses SRAM.
A2
TYPICAL CURRENT
CONSUMPTION
(1)
(1)
(2)
(2)
A4
DD
(3)
(3)
Case 1:
Case 2:
A5
I
I
Table
DD
DD
201
906
132
723
59
20
(A)
(A)
A6
3.
C1
V
2.5
2.5
2.5
(V)
DD
V
DD
3.3
3.3
3.3
V
(V)
DDCORE
(V)
2.5
2.5
2.5
5. Module: Low-Voltage Detect
6. Module: MSSPx (I
7. Module: Enhanced Universal
The LVDSTAT, V
is not implemented in this revision of silicon.
Work around
None.
Affected Silicon Revisions
If the module is in I
slave performs clock stretching, the first clock
pulse after the slave releases the SCLx line may
be narrower than the configured clock width.
This may result in the slave missing the first
clock in the next transmission/reception.
Work around
If the module is in I
the slave to perform clock stretching. Alter-
nately, the master can slow down the SCLx
clock frequency to a level where the slave can
detect the narrowed clock pulse.
Affected Silicon Revisions
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTA<1>) may not indicate when
the TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXIF flag
(PIR1<4>) to determine when new data can be
written to the TXREG register.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
Synchronous Asynchronous
Receiver Transmitter (EUSART)
A4
A4
A4
X
X
DDCORE
2
2011 Microchip Technology Inc.
C Master mode, do not allow
A5
A5
A5
2
X
X
2
C Master mode, and the
C™ Master)
status bit (WDTCON<6>),
A6
A6
A6
X
X
C1
C1
C1
X
X