PIC16F88-I/ML Microchip Technology, PIC16F88-I/ML Datasheet - Page 322

• Manufacturer Part Number: PIC16F88-I/ML
• Description: IC MCU FLASH 4KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details

PICmicro MID-RANGE MCU FAMILY
17.4.14
17.4.14.1 WCOL Status Flag
DS31017A-page 17-46
Stop Condition Timing
A stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop
sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held
low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the
SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one
T
pin is sampled high while SCL is high the P bit (SSPSTAT<4>) is set. A T
is cleared and the SSPIF bit is set
Whenever the firmware decides to take control of the bus, it will first determine if the bus is busy
by checking the S and P bits in the SSPSTAT register. If the bus is busy, then the CPU can be
interrupted (notified) when a Stop bit is detected (i.e. bus is free).
If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set
and the contents of the buffer are unchanged (the write doesn’t occur).
Figure 17-31: Stop Condition Receive or Transmit Mode
BRG
SCL
SDA
(baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA
Write to SSPCON2
Falling edge of
9th clock
Note: T
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup stop condition.
Preliminary
T
T
BRG
BRG
(Figure
T
SCL brought high after T
BRG
17-31).
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set
P
T
BRG
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
1997 Microchip Technology Inc.
BRG
later, the PEN bit
BRG