PIC16F88-I/SS Microchip Technology, PIC16F88-I/SS Datasheet - Page 394
![IC MCU FLASH 4KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F88-I/SS
Manufacturer Part Number
PIC16F88-I/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
8.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16F88-I/SS
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Data Rom Size
256 B
A/d Bit Size
10 bit
A/d Channels Available
7
Height
1.75 mm
Length
7.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F88-I/SS
Manufacturer:
U-BLOX
Quantity:
12 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- PIC16F87-IP PDF datasheet #7
- PIC16F88-ISO PDF datasheet #8
- Current page: 394 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
21.7
DS31021A-page 21-10
A/D Conversions
Example 21-2
inputs. The analog reference (V
conversion clock is F
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES
register will NOT be updated with the partially completed A/D conversion sample. That is, the
ADRES register will continue to contain the value of the last completed conversion (or the last
value written to the ADRES register). After the A/D conversion is aborted, a 2T
before the next acquisition is started. After this 2T
on the selected channel.
Example 21-2:
Figure 21-4: A/D Conversion T
;
;
;
;
Note:
Ensure that the required sampling time for the selected input
channel has elapsed. Then the conversion may be started.
BSF
CLRF
BSF
BCF
MOVLW
MOVWF
BCF
BSF
BSF
BSF
Set GO bit
T
:
:
:
AD
1 T
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D,
due to the required acquition time requirement.
Holding capacitor is disconnected
from analog input
show how to perform an A/D conversion. The I/O pins are configured as analog
STATUS, RP0
ADCON1
PIE1,
STATUS, RP0
0xC1
ADCON0
PIR1,
INTCON, PEIE
INTCON, GIE
ADCON0, GO
AD
b7
Doing an A/D Conversion
2 T
RC
. The conversion is performed on the AN0 channel.
AD
b6
ADIE
ADIF
3 T
AD
b5
REF
AD
4 T
) is the device V
Cycles
; Select Bank1
; Configure A/D inputs
; Enable A/D interrupts
; Select Bank0
; RC Clock, A/D is on, Channel 0 is selected
;
; Clear A/D interrupt flag bit
; Enable peripheral interrupts
; Enable all interrupts
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE
; bit is cleared upon completion of the
;
b4
AD
5 T
A/D Conversion.
Holding capacitor is connected to analog input
b3
AD
6 T
AD
DD
wait, an acquisition is automatically started
. The A/D interrupt is enabled, and the A/D
b2
AD
Next Q4: ADRES is loaded
7 T
AD
b1
8 T
GO bit is cleared
ADIF bit is set
1997 Microchip Technology Inc.
AD
b0
9 T
AD
b0
AD
10
wait is required
T
AD
11
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