PIC18LF1320-I/SS Microchip Technology, PIC18LF1320-I/SS Datasheet - Page 200
![IC MCU FLASH 4KX16 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC18LF1320-I/SS
Manufacturer Part Number
PIC18LF1320-I/SS
Description
IC MCU FLASH 4KX16 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
7.PIC18F1220-EP.pdf
(310 pages)
Specifications of PIC18LF1320-I/SS
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1320-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1220-ISO PDF datasheet #2
- PIC18F1220-ISO PDF datasheet #3
- PIC18F1220-ISO PDF datasheet #4
- PIC18F1220-ISO PDF datasheet #5
- PIC18F1220-ISO PDF datasheet #6
- PIC18F1220-EP PDF datasheet #7
- Current page: 200 of 308
- Download datasheet (5Mb)
PIC18F1220/1320
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605F-page 198
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit =
REG
W
Carry bit =
REG
W
Q1
=
=
=
=
register ‘f’
ADD W and Carry bit to f
[ label ] ADDWFC
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + (f) + (C) → dest
N, OV, C, DC, Z
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’, the
BSR will not be overridden.
1
1
ADDWFC
Read
Q2
0010
1
0x02
0x4D
0
0x02
0x50
00da
REG, W
Process
Data
Q3
ffff
f [,d [,a]]
destination
Write to
Q4
ffff
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Read literal
AND literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
The contents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
1
1
ANDLW
0000
Q2
‘k’
0xA3
0x03
© 2007 Microchip Technology Inc.
1011
0x5F
Process
Data
Q3
k
kkkk
Write to W
Q4
kkkk
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