PIC18LF1320-I/SS Microchip Technology, PIC18LF1320-I/SS Datasheet - Page 148
![IC MCU FLASH 4KX16 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC18LF1320-I/SS
Manufacturer Part Number
PIC18LF1320-I/SS
Description
IC MCU FLASH 4KX16 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
7.PIC18F1220-EP.pdf
(310 pages)
Specifications of PIC18LF1320-I/SS
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1320-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1220-ISO PDF datasheet #2
- PIC18F1220-ISO PDF datasheet #3
- PIC18F1220-ISO PDF datasheet #4
- PIC18F1220-ISO PDF datasheet #5
- PIC18F1220-ISO PDF datasheet #6
- PIC18F1220-EP PDF datasheet #7
- Current page: 148 of 308
- Download datasheet (5Mb)
PIC18F1220/1320
16.3.5
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The Frame Break character is
sent whenever the SENDB and TXEN bits (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loaded with data. Note that the value of data
written to TXREG will be ignored and all ‘0’s will be
transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 16-9 for the timing of the Break
character sequence.
16.3.5.1
The Enhanced USART module has the capability of
sending the Break signal that is required by the LIN bus
standard. The Break signal consists of a Start bit,
followed by twelve ‘0’ bits and a Stop bit. The Break sig-
nal is sent whenever the SENDB (TXSTA<3>) and
TXEN (TXSTA<5>) bits are set and TXREG is loaded
with data. The data written to TXREG will be ignored
and all ‘0’s will be transmitted.
SENDB is automatically cleared by hardware when the
Break signal has been sent. This allows the user to
preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal
transmission.
To send a Break Signal:
1.
2.
3.
DS39605F-page 146
Configure the EUSART for asynchronous trans-
missions (steps 1-5). Initialize the SPBRG register
for the appropriate baud rate. If a high-speed baud
rate is desired, set bit BRGH (see Section 16.2
“EUSART Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
BREAK CHARACTER SEQUENCE
Transmitting A Break Signal
4.
5.
6.
7.
See Figure 16-9 for the timing of the Break signal
sequence.
16.3.6
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (12 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 16.3.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
before placing the EUSART in its Sleep mode.
16.3.6.1
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
Set the SENDB bit.
Load a byte into TXREG. This triggers sending a
Break signal. The Break signal is complete
when TRMT is set. SENDB will also be cleared.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode. When the
TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
RECEIVING A BREAK CHARACTER
Transmitting a Break Sync
© 2007 Microchip Technology Inc.
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