PIC18F2321-I/SP Microchip Technology, PIC18F2321-I/SP Datasheet - Page 28

• Manufacturer Part Number: PIC18F2321-I/SP
• Description: IC PIC MCU FLASH 4KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2321-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F4321 FAMILY
2.6
The PIC18F4321 family of devices includes an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s
clock source. This may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected. The INTOSC output can also be
enabled when 31 kHz is selected, depending on the
INTSRC bit (OSCTUNE<7>).
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 31).
2.6.1
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs F
• In INTIO2 mode, OSC1 functions as RA7 and
FIGURE 2-8:
FIGURE 2-9:
DS39689E-page 26
while OSC1 functions as RA7 (see Figure 2-8) for
digital input and output.
OSC2 functions as RA6 (see Figure 2-9), both for
digital input and output.
F
OSC
RA7
RA7
RA6
/4
Internal Oscillator Block
INTIO MODES
INTIO1 OSCILLATOR MODE
INTIO2 OSCILLATOR MODE
I/O (OSC1)
I/O (OSC1)
OSC2
I/O (OSC2)
PIC18FXXXX
PIC18FXXXX
OSC
/4,
Preliminary
2.6.2
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa.
2.6.3
The INTOSC output has been calibrated at the
factory but can be adjusted in the user’s application.
This
(OSCTUNE<4:0>)
(Register 2-1).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTOSC clock will stabilize within 1 ms. Code execu-
tion continues during this shift. There is no indication
that the shift has occurred. The INTRC is not affected
by OSCTUNE.
The OSCTUNE register also implements the INTSRC
(OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits,
which control certain features of the internal oscillator
block. The INTSRC bit allows users to select which
internal oscillator provides the clock source when the
31 kHz frequency option is selected. This is covered in
greater detail in Section 2.7.1 “Oscillator Control
Register”.
The PLLEN bit controls the operation of the Phase
Locked Loop (PLL) in Internal Oscillator modes (see
Figure 2-10).
FIGURE 2-10:
CLKO
OSC2
INTOSC
is
INTOSC OUTPUT FREQUENCY
OSCTUNE REGISTER
done
RA6
(OSCTUNE<6>)
8 or 4 MHz
F
F
by
÷4
in
IN
OUT
PLLEN
INTOSC AND PLL BLOCK
DIAGRAM
© 2007 Microchip Technology Inc.
the
writing
Comparator
Loop
Filter
Phase
VCO
OSCTUNE
to
TUN4:TUN0
SYSCLK
register