DSPIC30F2011-20I/P Microchip Technology, DSPIC30F2011-20I/P Datasheet - Page 5
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DSPIC30F2011-20I/P
Manufacturer Part Number
DSPIC30F2011-20I/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
7.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Package
18PDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
12
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2011-20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2011-20I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.0
5.1
Once the programming executive has been verified
in memory (or loaded if not present), the dsPIC30F can
be programmed using the command set shown in
Table
provided in
Commands”.
TABLE 5-1:
A high-level overview of the programming process is
illustrated in
ing Enhanced ICSP mode. The chip is then bulk
erased, which clears all memory to ‘1’ and allows the
device to be programmed. The Chip Erase is verified
before programming begins. Next, the code memory,
data Flash and Configuration bits are programmed. As
these memories are programmed, they are each
verified to ensure that programming was successful. If
no errors are detected, the programming is complete
and Enhanced ICSP mode is exited. If any of the
verifications fail, the procedure should be repeated,
starting from the Chip Erase.
© 2010 Microchip Technology Inc.
SCHECK
READD
READP
PROGD
PROGP
PROGC
ERASEB
ERASED
ERASEP
QBLANK
QVER
Command
5-1. A detailed description for each command is
DEVICE PROGRAMMING
Overview of the Programming
Process
Figure
Section 8.0 “Programming Executive
Sanity check
Read data EEPROM, Configuration
registers and device ID
Read code memory
Program one row of data EEPROM
and verify
Program one row of code memory and
verify
Program Configuration bits and verify
Bulk Erase, or erase by segment
Erase data EEPROM
Erase code memory
Query if the code memory and data
EEPROM are blank
Query the software version
COMMAND SET SUMMARY
5-1. The process begins by enter-
Description
If Advanced Security features are enabled, then
individual Segment Erase operations need to be
performed, based on user selections (i.e., based on the
specific needs of the user application). The specific
operations that are used typically depend on the order
in which various segments need to be programmed for
a given application or system.
Section 5.2 “Entering Enhanced ICSP Mode”
through
describe the programming process in detail.
FIGURE 5-1:
Section 5.8 “Exiting Enhanced ICSP Mode”
Exit Enhanced ICSP
Program and verify
Configuration bits
Enter Enhanced
ICSP™ mode
Perform Chip
Configuration
Program and
Program and
default value
verify code
registers to
verify data
PROGRAMMING FLOW
Program
Finish
Start
Erase
Mode
DS70102K-page 5