PIC24HJ12GP202-I/SS Microchip Technology, PIC24HJ12GP202-I/SS Datasheet
PIC24HJ12GP202-I/SS
Specifications of PIC24HJ12GP202-I/SS
Available stocks
Related parts for PIC24HJ12GP202-I/SS
PIC24HJ12GP202-I/SS Summary of contents
Page 1
... Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-bit Microcontrollers Preliminary Data Sheet DS70282C ...
Page 2
... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Four processor exceptions On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
Page 4
... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN/SSOP Note: See Table 1 for the exact peripheral features per device. Preliminary © 2008 Microchip Technology Inc. ...
Page 5
... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Device PIC24HJ12GP201 PIC24HJ12GP202 Note 1: Only two out of three timers are remappable. 2: Only two out of three interrupts are remappable. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 ...
Page 6
... AN9/RP12 6 23 (1) /CN7/RB3 TMS/RP11 7 22 TDI/RP10 Vss DDCORE 10 Vss 19 (1) /CN1/RB4 TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 INT0/RP7 16 (1) /CN27/RB5 14 ASCL1/RP6 15 Preliminary /CN11/RB15 /CN12/RB14 /CN21/RB9 /CN22/RB8 /CN23/RB7 (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 © 2008 Microchip Technology Inc. ...
Page 7
... PGD1/EMUD1/AN2/RP0 /CN4/RB0 (1) PGC1/EMUC1/AN3/RP1 /CN5/RB1 (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 PIC24HJ12GP202 Preliminary (1) AN8/RP13 /CN13/RB13 (1) AN9/RP12 /CN14/RB12 (1) TMS/RP11 /CN15/RB11 (1) TDI/RP10 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70282C-page 6 Preliminary © 2008 Microchip Technology Inc. ...
Page 9
... Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 (MCU) Preliminary DS70282C-page 7 ...
Page 10
... DS70282C-page 8 Data Bus Data Latch X RAM Address Loop Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR UART1 CNx SPI1 I2C1 Preliminary PORTA PORTB 16 Remappable Pins © 2008 Microchip Technology Inc. ...
Page 11
... PGC3/EMUC3 I ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
Page 12
... Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2008 Microchip Technology Inc. ...
Page 13
... A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model PIC24HJ12GP201/202 is shown in Figure 2-2. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). ...
Page 14
... Control Signals to Various Blocks DS70282C-page 12 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2008 Microchip Technology Inc. ...
Page 15
... FIGURE 2-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
Page 16
... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70282C-page 14 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2008 Microchip Technology Inc. ...
Page 17
... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 18
... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. Preliminary © 2008 Microchip Technology Inc. ...
Page 19
... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 3.1 Program Address Space The program address PIC24HJ12GP201/202 devices is 4M instructions ...
Page 20
... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word (lsw Instruction Width Preliminary devices reserve the PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2008 Microchip Technology Inc. ...
Page 21
... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
Page 22
... Optionally Mapped into Program Memory 0xFFFF DS70282C-page 20 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 0x1FFFF 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2008 Microchip Technology Inc. ...
Page 23
TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
Page 24
... TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — ...
Page 25
TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
Page 26
TABLE 3-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
Page 27
TABLE 3-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
Page 28
... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
Page 29
TABLE 3-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
Page 30
... TABLE 3-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
Page 31
... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-17: PORTB REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
Page 32
TABLE 3-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
Page 33
... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 3.2.6 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
Page 34
... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary © 2008 Microchip Technology Inc. ...
Page 35
... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 3.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
Page 36
... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70282C-page 34 Program Counter 0 23 bits TBLPAG 1/0 8 bits 24 bits Select 1 PSVPAG 0 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2008 Microchip Technology Inc. ...
Page 37
... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
Page 38
... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2008 Microchip Technology Inc. ...
Page 39
... Using 1/0 Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ instructions (192 bytes time or a single program memory word, and erase program memory in blocks or ‘ ...
Page 40
... Operations” for further details. Preliminary stalls (waits) until the PROGRAMMING TIME T )% × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.05 1 0.00375 – 11064 Cycles = × × – – 1 0.05 1 0.00375 the user application must to Section 4.3 “Programming © 2008 Microchip Technology Inc. ...
Page 41
... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 — — ...
Page 42
... NVMKEY<7:0>: Key Register (write-only) bits DS70282C-page 40 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
Page 43
... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
Page 44
... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2008 Microchip Technology Inc. ...
Page 45
... V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 A simplified block diagram of the Reset module is shown in Figure 5-1. Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...
Page 46
... SWDTEN bit setting. DS70282C-page 44 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 47
... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (CONTINUED) ...
Page 48
... BOR BOR ) after a PWRT ensures that the system PWRT for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2008 Microchip Technology Inc. ...
Page 49
... BOR BOR extension time 100 μs maximum T BOR T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. POR ensures the voltage regulator output becomes stable ...
Page 50
... V BOR BOR PWRT BOR PWRT BOR PWRT Preliminary has elapsed. The delay BOR ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V PWRT DD trip point BOR V BOR V BOR V BOR © 2008 Microchip Technology Inc. ...
Page 51
... If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category ...
Page 52
... MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR © 2008 Microchip Technology Inc. ...
Page 53
... PIC24HJ12GP201/202 devices implement unique interrupts and 4 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1 ...
Page 54
... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70282C-page 52 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2008 Microchip Technology Inc. ...
Page 55
... Microchip Technology Inc. PIC24HJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
Page 56
... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2008 Microchip Technology Inc. ...
Page 57
... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 6.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt ...
Page 58
... The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70282C-page 56 (1) U-0 U-0 — — (3) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2008 Microchip Technology Inc. ...
Page 59
... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 ...
Page 60
... Unimplemented: Read as ‘0’ DS70282C-page 58 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 61
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — ...
Page 62
... Interrupt request has not occurred DS70282C-page 60 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 63
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282C-page 61 ...
Page 64
... Interrupt request has not occurred DS70282C-page 62 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 65
... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
Page 66
... Interrupt request not enabled DS70282C-page 64 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 67
... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282C-page 65 ...
Page 68
... Interrupt request not enabled DS70282C-page 66 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 69
... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
Page 70
... Interrupt is priority 1 000 = Interrupt source is disabled DS70282C-page 68 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 71
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 72
... Interrupt is priority 1 000 = Interrupt source is disabled DS70282C-page 70 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 73
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
Page 74
... Interrupt is priority 1 000 = Interrupt source is disabled DS70282C-page 72 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 75
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
Page 76
... Unimplemented: Read as ‘0’ DS70282C-page 74 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 77
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
Page 78
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70282C-page 76 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 79
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 80
... PIC24HJ12GP201/202 NOTES: DS70282C-page 78 Preliminary © 2008 Microchip Technology Inc. ...
Page 81
... Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 7-2 for PLL details © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed ...
Page 82
... This factor is selected using the PLLPOST<1:0> PLL bits (CLKDIV<7:6>). ‘N2’ can be either and must be selected such that the PLL output frequency ( the range of 12.5 MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. Preliminary © 2008 Microchip Technology Inc. Configuration bits, is divided OSC ). ...
Page 83
... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 ’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a IN VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...
Page 84
... Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70282C-page 82 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 85
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 ...
Page 86
... DS70282C-page 84 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 87
... Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — ...
Page 88
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Preliminary and the CF © 2008 Microchip Technology Inc. ...
Page 89
... EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 8.2 Instruction-Based Power-Saving Modes PIC24HJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 90
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible © 2008 Microchip Technology Inc. ...
Page 91
... SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 U-0 T2MD T1MD — U-0 ...
Page 92
... Output Compare 1 module is enabled DS70282C-page 90 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 93
... CK WR Port Data Latch Read LAT Read Port © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled ...
Page 94
... CNPU2 registers, which contain the control bits for No each of the CN pins. Setting any of the control bits No enables the weak pull-ups for the corresponding pins. No Note: Pull-ups on change notification pins No should always be disabled when the port pin is configured as a digital output. Preliminary © 2008 Microchip Technology Inc. ...
Page 95
... FIGURE 9-2: REMAPPABLE MUX INPUT FOR U1RX RP0 RP1 RP2 RP 15 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 9.4.2 CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral’ ...
Page 96
... RPINR7 IC2 RPINR7 IC7 RPINR10 IC8 RPINR10 OCFA RPINR11 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1IN RPINR20 SS1IN RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2008 Microchip Technology Inc. ...
Page 97
... SDO1 SCK1OUT SS1OUT OC1 OC2 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-3 and Figure 9-3). The list of peripherals for output mapping also includes a null value of ‘ ...
Page 98
... IOLOCK bit from being cleared after it has been set once. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. Preliminary © 2008 Microchip Technology Inc. ...
Page 99
... INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — ...
Page 100
... Input tied to RP1 00000 = Input tied to RP0 DS70282C-page 98 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR< ...
Page 102
... Input tied to RP1 00000 = Input tied to RP0 DS70282C-page 100 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 103
... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R< ...
Page 104
... Input tied to RP0 DS70282C-page 102 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 105
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR< ...
Page 106
... Input tied to RP1 00000 = Input tied to RP0 DS70282C-page 104 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 107
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R< ...
Page 108
... Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 109
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-3 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 ...
Page 110
... Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 111
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-3 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 ...
Page 112
... PIC24HJ12GP201/202 NOTES: DS70282C-page 110 Preliminary © 2008 Microchip Technology Inc. ...
Page 113
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the To TCKPS< ...
Page 114
... Unimplemented: Read as ‘0’ DS70282C-page 112 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 115
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an generated with the Timer3 interrupt flags. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 11.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: 1. Set the corresponding T32 control bit. ...
Page 116
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70282C-page 114 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2008 Microchip Technology Inc. ...
Page 117
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70282C-page 115 ...
Page 118
... Note 1: In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70282C-page 116 U-0 U-0 — — R/W-0 R/W-0 (1) T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 119
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 (1) — — ...
Page 120
... PIC24HJ12GP201/202 NOTES: DS70282C-page 118 Preliminary © 2008 Microchip Technology Inc. ...
Page 121
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 • Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin ...
Page 122
... Input capture module turned off DS70282C-page 120 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 123
... TMR3 TMR2 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 value matches the compare register value. The Output Compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. The Output Compare module can also generate interrupts on compare match events ...
Page 124
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2008 Microchip Technology Inc. ...
Page 125
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 126
... PIC24HJ12GP201/202 NOTES: DS70282C-page 124 Preliminary © 2008 Microchip Technology Inc. ...
Page 127
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions ...
Page 128
... DS70282C-page 126 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 129
... MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 DISSCK ...
Page 130
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70282C-page 128 Preliminary © 2008 Microchip Technology Inc. ...
Page 131
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 132
... PIC24HJ12GP201/202 NOTES: DS70282C-page 130 Preliminary © 2008 Microchip Technology Inc. ...
Page 133
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 15.1 Operating Modes The hardware fully implements all the master and slave 2 functions of the I C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing ...
Page 134
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2008 Microchip Technology Inc. ...
Page 135
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 136
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70282C-page 134 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) Preliminary © 2008 Microchip Technology Inc. ...
Page 137
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 R/C-0 HS — ...
Page 138
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70282C-page 136 2 C slave device address byte. Preliminary © 2008 Microchip Technology Inc. ...
Page 139
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 140
... PIC24HJ12GP201/202 NOTES: DS70282C-page 138 Preliminary © 2008 Microchip Technology Inc. ...
Page 141
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 • Fully Integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 1 Mbps to 15 bps at 16x mode at 40 MIPS • ...
Page 142
... DS70282C-page 140 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 143
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 MODE REGISTER (CONTINUED) x Preliminary DS70282C-page 141 ...
Page 144
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 145
... UxRSR to the empty state. bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
Page 146
... PIC24HJ12GP201/202 NOTES: DS70282C-page 144 Preliminary © 2008 Microchip Technology Inc. ...
Page 147
... There is only one sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Depending on the particular device pinout, the ADC can have analog input pins, designated AN0 through AN9. In addition, there are two analog input pins for external voltage reference connections ...
Page 148
... REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. DS70282C-page 146 Preliminary (1) ( REF DD REF SS ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2008 Microchip Technology Inc. ...
Page 149
... FIGURE 17-2: ADC BLOCK DIAGRAM FOR PIC24HJ12GP202 AN0 AN9 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V - REF CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN7 V - REF CH123NA CH123NB AN2 AN5 CH123SA ...
Page 150
... Note 1: Refer to Figure 7-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, F the clock source frequency See the ADC electrical characteristics for the exact RC clock value. DS70282C-page 148 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 = 1/F . OSC OSC Preliminary AD1CON3<15> equal to OSC © 2008 Microchip Technology Inc. ...
Page 151
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — ...
Page 152
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in prog- ress. Automatically cleared by hardware at start of a new conversion. DS70282C-page 150 Preliminary © 2008 Microchip Technology Inc. ...
Page 153
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — ...
Page 154
... T · (ADCS<7:0> · 00000000 = T · (ADCS<7:0> · DS70282C-page 152 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 155
... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 156
... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 157
... Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 PIC24HJ12GP202 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © ...
Page 158
... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24HJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 159
... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24HJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 © ...
Page 160
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1,2) R/W-0 R/W-0 CSS9 CSS8 bit 8 R/W-0 R/W-0 CSS1 CSS0 bit Bit is unknown (1,2) R/W-0 R/W-0 PCFG9 PCFG8 bit 8 R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown SS © 2008 Microchip Technology Inc. ...
Page 161
... FUID2 0xF80016 FUID3 Note 1: Reserved bits read as ‘1’ and must be programmed as ‘1’. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 18.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
Page 162
... Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Preliminary © 2008 Microchip Technology Inc. ...
Page 163
... COE FICD JTAGEN FICD ICS<1:0> FICD © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect Watchdog Timer enabled/disabled by user software (LPRC can be ...
Page 164
... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device (1,2) should V fall below the BOR threshold voltage Preliminary . The main purpose of the BOR DDCORE © 2008 Microchip Technology Inc. ...
Page 165
... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 18.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
Page 166
... BS = 256 IW 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h GS = 3584 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 768 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 1792 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 2048 IW 001FFEh © 2008 Microchip Technology Inc. ...
Page 167
... Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGC1/EMUC1 and PGD1/EMUD1 • PGC2/EMUC2 and PGD2/EMUD2 • PGC3/EMUC3 and PGD3/EMUD3 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 18.8 In-Circuit Debugger ® When MPLAB circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE ...
Page 168
... PIC24HJ12GP201/202 NOTES: DS70282C-page 166 Preliminary © 2008 Microchip Technology Inc. ...
Page 169
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • ...
Page 170
... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS70282C-page 168 Description Preliminary © 2008 Microchip Technology Inc. ...
Page 171
... BTG BTG f,#bit4 BTG Ws,#bit4 10 BTSC BTSC f,#bit4 BTSC Ws,#bit4 11 BTSS BTSS f,#bit4 BTSS Ws,#bit4 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND .AND .AND. lit5 ...
Page 172
... Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to address Go to indirect Preliminary © 2008 Microchip Technology Inc Status Flags Words Cycles Affected 1 ...
Page 173
... POP.D Wnd POP.S 45 PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S 46 PWRSAV PWRSAV #lit1 © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG = WREG = .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR .IOR .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f ...
Page 174
... WREG – f WREG = WREG – – lit5 – WREG – f – (C) WREG = WREG – f – ( – Wb – ( lit5 – Wb – ( nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Preliminary © 2008 Microchip Technology Inc Status Flags Words Cycles Affected 1 2 None 1 2 None ...
Page 175
... XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary ...
Page 176
... PIC24HJ12GP201/202 NOTES: DS70282C-page 174 Preliminary © 2008 Microchip Technology Inc. ...
Page 177
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 20.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 178
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2008 Microchip Technology Inc. ...
Page 179
... REAL ICE offers significant advantages over competi- tive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 20.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 180
... IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2008 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 181
... Maximum allowable current is a function of device maximum power dissipation (see Table 21-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGDx pins, which are able to sink/source 12 mA. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 .................................................................................. -0.3V to +5.6V SS ...
Page 182
... PIC24HJ12GP201/202 40 40 Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 45 — °C — °C — °C — °C — °C — °C/W 1 © 2008 Microchip Technology Inc. ...
Page 183
... Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3 ...
Page 184
... OSC1 DD Preliminary 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS . SS © 2008 Microchip Technology Inc. ...
Page 185
... Base I current is measured with core off, clock on and all modules turned off. Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to V © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 186
... Preliminary ) PD (3,4) Base Power-Down Current Watchdog Timer Current: ΔI (3) WDT ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS © 2008 Microchip Technology Inc. ...
Page 187
... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See Table 9-1 for a list of digital-only and analog pins. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 188
... DD core voltage DD Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 2mA 3. 2mA 3. -2 -1 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions 2.55 V © 2008 Microchip Technology Inc. ...
Page 189
... TABLE 21-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristics No. C External Filter Capacitor EFC Value © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
Page 190
... OSC2 output Min Typ Max — — 15 — — 50 — — 400 Preliminary ≤ +85°C for Industrial ≤ +125°C for Extended Units Conditions and HS modes when external clock is used to drive OSC1 pF EC mode C™ mode © 2008 Microchip Technology Inc. ...
Page 191
... OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Q2 Q3 ...
Page 192
... MHz ECPLL and XTPLL modes MHz ms % Measured over 100 ms period ≤ +85°C for Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. 1). See Section 18.4 “Watchdog © 2008 Microchip Technology Inc. ...
Page 193
... INTx Pin High or Low Time (output) INP DI40 T CNx High or Low Time (input) RBP Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 194
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 21-1 for load conditions. DS70282C-page 192 SY10 SY20 SY13 Preliminary © 2008 Microchip Technology Inc. SY13 ...
Page 195
... Fail-Safe Clock Monitor Delay FSCM Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 196
... Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 — © 2008 Microchip Technology Inc. ...
Page 197
... TC15 TtxP TxCK Input Period Synchronous, TC20 T - Delay from External TxCK Clock CKEXT Edge to Timer Increment MRL © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 — ...
Page 198
... Industrial ≤ +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See parameter D032 ns See parameter D031 © 2008 Microchip Technology Inc. ...
Page 199
... Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. PIC24HJ12GP201/202 OC20 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 200
... Conditions See Note 3 — ns — ns See Note 3 — ns See parameter D032 and Note 4 — ns See parameter D031 and Note 4 — ns See parameter D032 and Note 4 — ns See parameter D031 and Note — — ns — — ns — © 2008 Microchip Technology Inc. ...