PIC16LF87-I/P Microchip Technology, PIC16LF87-I/P Datasheet - Page 3

• Manufacturer Part Number: PIC16LF87-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF87-I/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3. Module: Internal RC Oscillator
4. Module: PORTB Pull-ups
© 2008 Microchip Technology Inc.
When any one of the seven INTOSC frequencies
is enabled by the following conditions, it is possible
for the oscillator to overshoot the selected
frequency:
1. A clock switch from INTRC (31 kHz) to an
2. Exit from Sleep mode with the IRCF bits
3. Executing a clock source switch via the SCS
If the selected frequency is 8 MHz, then the
voltage versus frequency specification of the
device may be violated.
Work around
When it is required for the application to run at
8 MHz, it is recommended that the application
does not start executing code at 8 MHz until the
60 ms firmware delay (see issue
completed. During the 60 ms settling period, the
application can execute code up to 4 MHz. Upon
completion of the 60 ms firmware delay, the 8 MHz
can be selected via the IRCF bits.
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.
When RBPU = 0 (OPTION_REG register), the
PORTB weak pull-ups will not be disabled by the
input functions of the SSP and/or CCP (Capture
mode) module as indicated by the RB<5:1> I/O
block diagrams in Section 5.0 “I/O Ports”.
Work around
1. If the SSP and/or CCP (Capture mode) module
OR
2. If the SSP and/or CCP (Capture mode) module
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.
INTOSC (125 kHz-8 MHz) frequency via the
IRCF bits (OSCCON register).
already configured for an INTOSC frequency.
bits (OSCCON register) to the internal RC
oscillator with the IRCF bits already configured
for an INTOSC frequency.
is enabled, do not enable the PORTB weak
pull-ups and use external pull-up resistors.
and PORTB pull-ups are enabled, then evalu-
ate the functionality of the SSP (I
CCP (Capture mode) module to ensure proper
operation within your application.
2
C™/SPI) or
2)
has
5. Module: PORTB
A delay of 1 T
modifies the contents of PORTB simultaneously
occurs when any of the following modules (if
enabled) execute an operation that effects the
signals on their respective PORTB I/O pins.
CCP Module:
PWM Mode (CCP1CON<3:0> = 11xx)
When CCP1CON<5:4> bits = 10, the PWM output
signal will be delayed by 1 T
to modify the contents of PORTB is executed.
SSP Module:
SPI Slave Modes (SSPCON<3:0> =
Clock signal is derived from an external source.
Transmission of data (SDO pin) will be delayed by
1 T
of PORTB is executed. Reception of data is not
affected.
AUSART Module:
Synchronous Slave Mode (TXSTA<7> = 0)
Clock signal is derived from an external source.
Transmission of data (TX pin) will be delayed by
1 T
of PORTB is executed. Reception of data is not
affected.
Work around
None
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.
OSC
OSC
when an instruction to modify the contents
when an instruction to modify the contents
OSC
PIC16F87/88
will occur if an instruction that
OSC
when an instruction
DS80171L-page 3
0100
and
0101
)