AT90PWM3-16MQ Atmel, AT90PWM3-16MQ Datasheet - Page 66

• Manufacturer Part Number: AT90PWM3-16MQ
• Description: IC AVR MCU FLASH 8K 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16MQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3
66
Alternate Port Functions
AT90PWM2/3/2B/3B
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 11-5. Alternate Port Functions
Note:
Table 11-2
ure 11-5
in the modules having the alternate function.
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Pxn
are not shown in the succeeding tables. The overriding signals are generated internally
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
summarizes the function of the overriding signals. The pin and port indexes from
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
SLEEP: SLEEP CONTROL
1
0
1
0
1
0
1
0
(1)
PUOExn
PUOVxn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
SYNCHRONIZER
D
L
SET
CLR
Q
Q
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
WDx: WRITE DDRx
WRx: WRITE PORTx
PUD: PULLUP DISABLE
WPx: WRITE PINx
clk
DIxn: DIGITAL INPUT PIN n ON PORTx
RDx: READ DDRx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
D
PINxn
I/O
CLR
Figure 11-2
: I/O CLOCK
Q
Q
RESET
PORTxn
RESET
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
can be overridden by
1
0
clk
PUD
WDx
RRx
DIxn
AIOxn
RDx
RPx
I/O
WRx
4317J–AVR–08/10
Figure 11-5
PTOExn
WPx
Fig-
I/O
,