ATMEGA8515L-8AU Atmel, ATMEGA8515L-8AU Datasheet - Page 150

• Manufacturer Part Number: ATMEGA8515L-8AU
• Description: IC AVR MCU 8K 8MHZ 3V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Asynchronous Operational
Range
150
ATmega8515(L)
Figure 70 shows the sampling of the stop bit and the earliest possible beginning of the
start bit of the next frame.
Figure 70. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If
the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after
the last of the bits used for majority voting. For Normal Speed mode, the first low level
sample can be at point marked (A) in Figure 70. For Double Speed mode the first low
level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-
tion influences the operational range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the
received bit rate and the internally generated baud rate. If the Transmitter is sending
frames at too fast or too slow bit rates, or the internally generated baud rate of the
Receiver does not have a similar (see Table 61) base frequency, the Receiver will not
be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and
internal Receiver baud rate.
D
S
S
S
R
Table 61 and Table 62 list the maximum Receiver baud rate error that can be tolerated.
Note that Normal Speed mode has higher toleration of baud rate variations.
(U2X = 0)
(U2X = 1)
Sample
Sample
F
M
slow
RxD
Sum of character size and parity size (D = 5- to 10-bit).
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
Receiver baud rate. R
accepted in relation to the Receiver baud rate.
M
R
= 5 for Double Speed mode.
slow
=
------------------------------------------ -
S 1
1
1
–
2
(
D
+
+
D S ⋅
3
2
1
fast
)S
4
+
is the ratio of the fastest incoming data rate that can be
S
5
3
F
6
7
4
8
STOP 1
9
5
10
F
(A)
0/1
R
6
= 8 for Normal Speed and S
M
fast
= 9 for Normal Speed and
0/1
=
0/1
0/1
(B)
-----------------------------------
(
D
(
+
D
1
+
)S
2
)S
+
S
2512K–AVR–01/10
M
(C)
F
= 4