AT90USB82-16MU Atmel, AT90USB82-16MU Datasheet - Page 190

• Manufacturer Part Number: AT90USB82-16MU
• Description: IC AVR MCU 8K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB82-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.5
19.5.1
19.5.2
19.5.3
19.6
190
Power modes
Memory management
AT90USB82/162
Idle mode
Power down
Freeze clock
In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the
USB controller is running or not. The CPU can wake up on any USB interrupts.
In this mode, the oscillator is stopped and halts all the clocks (CPU and peripherals). The USB
controller “wakes up” when:
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
Moreover, when FRZCLK is set, only the asynchronous interrupt may be triggered :
The controller does only support the following memory allocation management.
The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last
Endpoint). The firmware shall thus configure them in the same order.
The reservation of an Endpoint “k
cates the memory and insert it between the Endpoints “k
memory “slides” up and its data is lost. Note that the “k
slide.
Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration
(EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the
“k
memory does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
• the WAKEUPI interrupt is triggered (single asynchronous interrupt)
• USBCON,
• DPRAM direct access registers (DPADD7:0, UEDATX)
• UDCON (detach, ...)
• UDINT
• UDIEN
• WAKEUPI
i+1
” Endpoint memory automatically “slides” down. Note that the “k
i
” is done when its ALLOC bit is set. Then, the hardware allo-
i+2
” and upper Endpoint memory does not
i-1
” and “k
i+1
i+2
”. The “k
” and upper Endpoint
7707F–AVR–11/10
i+1
” Endpoint