AT90USB82-16MU Atmel, AT90USB82-16MU Datasheet - Page 143
AT90USB82-16MU
Manufacturer Part Number
AT90USB82-16MU
Description
IC AVR MCU 8K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB82-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Controller Family/series
AVR USB
No. Of I/o's
22
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
16MHz
Rohs Compliant
Yes
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Package
32QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB82-16MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 143 of 307
- Download datasheet (4Mb)
16.1.4
7707F–AVR–11/10
SPI Status Register – SPSR
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 16-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 16-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 16-4.
• Bit 7 – SPIF: SPI Interrupt Flag
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPHA
CPOL
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
7
SPIF
R
0
0
1
0
1
Figure 16-3
6
WCOL
R
0
SPR1
0
0
1
1
0
0
1
1
and
5
–
R
0
Figure 16-4
Figure 16-3
Leading Edge
Leading Edge
4
–
R
0
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is sum-
and
3
–
R
0
Figure 16-4
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
2
–
R
0
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
AT90USB82/162
for an example. The CPOL
1
–
R
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
0
SPI2X
R/W
0
SPSR
osc
143
is
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