PIC24FJ32GA002-I/SS Microchip Technology, PIC24FJ32GA002-I/SS Datasheet - Page 14

• Manufacturer Part Number: PIC24FJ32GA002-I/SS
• Description: IC PIC MCU FLASH 32K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ32GA002-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
37. Module: I
38. Module: I
39. Module: UART
DS80470E-page 14
Under certain circumstances, a module operating in
Slave mode may not respond correctly to some of
the special addresses reserved by the I
This happens when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
• bits, A<7:1>, of the slave address
In these cases, the Slave module Acknowledges
the command and triggers an I
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
The Transmit Buffer Full flag, TBF (I2CxSTAT<0>),
may not be cleared by hardware if a collision on
the I
edge during a transmission.
Work around
None.
Affected Silicon Revisions
When the UART is operating using two Stop bits
(STSEL = 1), it may sample the first Stop bit
instead of the second one. If the device being
communicated with is one using one Stop bit in its
communications, this may lead to framing errors.
Work around
None.
Affected Silicon Revisions
A3/
A3/
A3/
A4
A4
A4
and
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
‘0000xxx’.
X
X
X
2
C bus occurs before the first falling clock
B4
B4
B4
X
X
2
2
C (Slave Mode)
C
B5
B5
B5
X
X
B8
B8
B8
X
X
2
C slave interrupt; it
2
C protocol.
40. Module: Oscillator (SOSC)
41. Module: Voltage Regulator
42. Module: Core (Code Protection)
The
selected by the SOSCSEL Configuration bits
(CW2<12:11>), is not available in this silicon revi-
sion. The oscillator in all devices functions in the
Default (High-Gain) mode only.
Work around
None.
Affected Silicon Revisions
The Standby mode wake-up option, selected by
the WUTSEL Configuration bits (CW2<14:13>), is
not available in this silicon revision. All devices use
the default regulator wake-up time of 190 s.
Work around
None.
Affected Silicon Revisions
When General Segment Code Protection has
been enabled (GCP Configuration bit is pro-
grammed), applications are unable to write to the
first 512 bytes of the program memory space
(0000h through 0200h). In applications that may
require the interrupt vectors to be changed during
run time, such as bootloaders, modifications to the
Interrupt Vector Tables (IVTs) will not be possible.
Work around
Create two new Interrupt Vector Tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
A3/
A3/
A3/
A4
A4
A4
X
X
low-power
B4
B4
B4
X
B5
B5
B5
secondary
 2010 Microchip Technology Inc.
B8
B8
B8
oscillator
option,