PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 398

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F85J11 FAMILY
External Memory Bus ......................................................... 99
External Oscillator Modes .................................................. 39
F
Fail-Safe Clock Monitor ............................................ 279, 291
Fast Register Stack ............................................................ 69
Firmware Instructions ....................................................... 299
Flash Configuration Words
Flash Program Memory ...................................................... 89
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 320
H
Hardware Multiplier .......................................................... 111
DS39774D-page 398
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Data Width Modes ......................................... 102
16-Bit Mode Timing .................................................. 106
16-Bit Word Write Mode ........................................... 104
21-Bit Addressing ..................................................... 101
8-Bit Data Width Mode ............................................. 107
8-Bit Mode Timing .................................................... 108
Address and Data Line Usage (table) ...................... 101
Address and Data Width .......................................... 101
Address Shifting ....................................................... 101
and Program Memory Modes .................................. 102
Control ..................................................................... 100
I/O Port Functions ...................................................... 99
Operation in Power-Managed Modes ...................... 109
Wait States ............................................................... 102
Weak Pull-ups on Port Pins ..................................... 102
EC Modes .................................................................. 40
HS Modes .................................................................. 39
Exiting Fail-Safe Operation ...................................... 292
Interrupts in Power-Managed Modes ....................... 292
POR or Wake-up From Sleep .................................. 292
WDT During Oscillator Failure ................................. 291
Mapping ................................................................... 279
Associated Registers ................................................. 97
Control Registers ....................................................... 90
Erase Sequence ........................................................ 94
Erasing ....................................................................... 94
Operation During Code-Protect ................................. 97
Reading ...................................................................... 93
Table Pointer
Table Pointer Boundaries .......................................... 92
Table Reads and Table Writes .................................. 89
Write Sequence ......................................................... 95
Writing ........................................................................ 95
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
EECON1 and EECON2 ..................................... 90
TABLAT (Table Latch) Register ......................... 92
TBLPTR (Table Pointer) Register ...................... 92
Boundaries Based on Operation ........................ 92
Unexpected Termination .................................... 97
Write Verify ........................................................ 97
I
I/O Ports ........................................................................... 129
I
INCF ................................................................................ 320
INCFSZ ............................................................................ 321
In-Circuit Debugger .......................................................... 293
In-Circuit Serial Programming (ICSP) ...................... 279, 293
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 346
Indirect Addressing ............................................................ 83
INFSNZ ............................................................................ 321
Initialization Conditions for all Registers ...................... 57–61
Instruction Cycle ................................................................ 70
Instruction Set .................................................................. 299
2
C Mode (MSSP) ............................................................ 188
Input Pins and Voltage Considerations .................... 129
Open-Drain Outputs ................................................. 130
Output Pin Drive ...................................................... 129
Pin Capabilities ........................................................ 129
Pull-up Configuration ............................................... 130
Acknowledge Sequence Timing .............................. 216
Associated Registers ............................................... 222
Baud Rate Generator .............................................. 209
Bus Collision
Clock Arbitration ...................................................... 210
Clock Stretching ....................................................... 202
Clock Synchronization and the CKP Bit ................... 203
Effects of a Reset .................................................... 217
General Call Address Support ................................. 206
I
Master Mode ............................................................ 207
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 217
Operation ................................................................. 193
Read/Write Bit Information (R/W Bit) ............... 193, 195
Registers ................................................................. 188
Serial Clock (SCK/SCL) ........................................... 195
Slave Mode .............................................................. 193
Sleep Operation ....................................................... 217
Stop Condition Timing ............................................. 216
and Standard PIC18 Instructions ............................. 346
Clocking Scheme ....................................................... 70
Flow/Pipelining ........................................................... 70
ADDLW .................................................................... 305
ADDWF .................................................................... 305
ADDWF (Indexed Literal Offset Mode) .................... 347
2
C Clock Rate w/BRG ............................................. 209
During a Repeated Start Condition .................. 220
During a Stop Condition .................................. 221
10-Bit Slave Receive Mode (SEN = 1) ............ 202
10-Bit Slave Transmit Mode ............................ 202
7-Bit Slave Receive Mode (SEN = 1) .............. 202
7-Bit Slave Transmit Mode .............................. 202
Baud Rate Generator ...................................... 209
Operation ......................................................... 208
Reception ........................................................ 213
Repeated Start Condition Timing .................... 212
Start Condition Timing ..................................... 211
Transmission ................................................... 213
and Arbitration ................................................. 217
Addressing ....................................................... 193
Addressing Masking ........................................ 194
Reception ........................................................ 195
Transmission ................................................... 195
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