PIC18LF25J11-I/SS Microchip Technology, PIC18LF25J11-I/SS Datasheet - Page 453
![IC PIC MCU FLASH 32K 2V 28-SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF25J11-I/SS
Manufacturer Part Number
PIC18LF25J11-I/SS
Description
IC PIC MCU FLASH 32K 2V 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18LF25J11-I/SS
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
=
=
register ‘f’
Subtract Literal from FSR
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
1
1
SUBFSR 2, 23h
Read
1110
Q2
03FFh
03DCh
1001
Process
Data
Q3
ffkk
destination
Write to
kkkk
Q4
PIC18F46J11 FAMILY
SUBULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
No
FSR2
PC
FSR2
PC
Q1
Subtract Literal from FSR2 and Return
SUBULNK k
0 ≤ k ≤ 63
FSR2 – k → FSR2,
(TOS) → PC
None
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
1
2
=
=
=
=
1110
Operation
register ‘f’
SUBULNK 23h
Read
No
Q2
03FFh
0100h
03DCh
(TOS)
1001
Operation
Process
Data
No
Q3
DS39932C-page 453
11kk
destination
Operation
Write to
kkkk
No
Q4
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