PIC18LF25J11-I/SS Microchip Technology, PIC18LF25J11-I/SS Datasheet - Page 104
![IC PIC MCU FLASH 32K 2V 28-SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF25J11-I/SS
Manufacturer Part Number
PIC18LF25J11-I/SS
Description
IC PIC MCU FLASH 32K 2V 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18LF25J11-I/SS
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 104 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
EXAMPLE 6-3:
DS39932C-page 104
ERASE_BLOCK
RESTART_BUFFER
FILL_BUFFER
WRITE_BUFFER
WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
Required
Sequence
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
...
MOVLW
MOVWF
MOVFF
MOVWF
TBLWT+*
DECFSZ COUNTER
BRA
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
DECFSZ WRITE_COUNTER
BRA
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
D’64
COUNTER
POSTINC0, WREG
TABLAT
WRITE_BYTE_TO_HREGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
RESTART_BUFFER
; Load TBLPTR with the base address
; of the memory block, minus 1
; enable write to memory
; enable Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
; point to buffer
; read the new data from I2C, SPI,
; PSP, USART, etc.
; number of bytes in holding register
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
; done with one write cycle
; if not done replacing the erase block
© 2009 Microchip Technology Inc.
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