ATTINY84-20PU Atmel, ATTINY84-20PU Datasheet - Page 159
ATTINY84-20PU
Manufacturer Part Number
ATTINY84-20PU
Description
IC MCU AVR 8K FLASH 20MHZ 14-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY84-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Package
14PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY84-20PU
Manufacturer:
XILINX
Quantity:
25
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19. Memory Programming
19.1
8006K–AVR–10/10
Program And Data Memory Lock Bits
This section describes the different methods for programming ATtiny24/44/84 memories.
The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional security listed in
erased to “1” with the Chip Erase command.
The device has no separate boot loader section. The SPM instruction is enabled for the whole
Flash, if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled.
Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro-
grammed, even if lock bits are set. Thus, when lock bit security is required, debugWIRE should
always be disabled by clearing the DWEN fuse.
Table 19-1.
Note:
Table 19-2.
Notes:
Lock bits can also be read by device firmware. See section
Data from Software” on page
LB2
LB1
LB Mode
Memory Lock Bits
1
2
3
“1” means unprogrammed, “0” means programmed.
1. Program fuse bits before programming LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
Lock Bit
Lock Bit Byte
Lock Bit Protection Modes.
LB2
1
1
0
(1) (2)
LB1
155.
1
0
0
Bit No
7
6
5
4
3
2
1
0
Protection Type
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
High-voltage and Serial Programming mode. The Fuse bits are
locked in both Serial and High-voltage Programming mode.
debugWire is disabled.
Further programming and verification of the Flash and EEPROM
is disabled in High-voltage and Serial Programming mode. The
Fuse bits are locked in both Serial and High-voltage
Programming mode.
Description
–
–
–
–
–
–
Lock bit
Lock bit
(1)
Table
debugWire is disabled.
“Reading Lock, Fuse and Signature
19-2. The lock bits can only be
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
ATtiny24/44/84
(1)
159
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