PIC16F72-I/SO Microchip Technology, PIC16F72-I/SO Datasheet - Page 58

• Manufacturer Part Number: PIC16F72-I/SO
• Description: IC PIC MCU FLASH 2KX14 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 8-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F72
10.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (R
switch (R
required to charge the capacitor C
switch (R
(V
at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, T
the PICmicro™ Mid-Range MCU Reference Manual,
(DS33023). In general, however, given a max of 10 kΩ
and at a temperature of 100°C, T
than 16 µs.
10.2
The A/D conversion time per bit is defined as T
A/D conversion requires 9.0 T
The source of the A/D conversion clock is software
selectable. The four possible options for T
For correct A/D conversions, the A/D conversion clock
(T
as small as possible, but no less than 1.6 µs and not
greater than 6.4 µs.
Table 10-1 shows the resultant T
the device operating frequencies and the A/D clock
source selected.
TABLE 10-1:
DS39597B-page 56
Note 1: The RC source has a typical T
AD
DD
• 2 T
• 8 T
• 32 T
• Internal RC oscillator (2 - 6 µs)
) must be selected to ensure a minimum T
). The source impedance affects the offset voltage
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
A/D Acquisition Requirements
Selecting the A/D Conversion
Clock
SS
OSC
OSC
SS
recommended for SLEEP operation.
OSC
) impedance varies over the device voltage
) impedance directly affect the time
Operation
32 T
RC
2 T
8 T
T
OSC
OSC
(1, 2)
AD
OSC
vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
S
) and the internal sampling
AD Clock Source (T
AD
HOLD
AD
per 8-bit conversion.
ACQ
HOLD
times derived from
) must be allowed
will be no more
. The sampling
AD
AD
time of 4 µs, but can vary between 2-6 µs.
are:
ACQ
AD
AD
, see
. The
AD
time
)
ADCS<1:0>
00
01
10
11
10.3
The ADCON1, and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (V
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
10.4
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
on the selected channel. The GO/DONE bit can then
be set to start the conversion.
Note:
Note 1: When reading the port register, all pins
AD
Configuring Analog Port Pins
A/D Conversions
2: Analog levels on any pin that is defined as
wait, an acquisition is automatically started
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
a digital input (including the AN4:AN0
pins), may cause the input buffer to
consume current out of the device
specification.
OH
Maximum Device Frequency
 2002 Microchip Technology Inc.
or V
OL
) will be converted.
1.25 MHz
(Note 1)
20 MHz
5 MHz
Max.
AD
wait