PIC12C672-10I/P Microchip Technology, PIC12C672-10I/P Datasheet - Page 147
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12C672-10I/P
Manufacturer Part Number
PIC12C672-10I/P
Description
IC MCU OTP 2KX14 A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
1
Digital Ic Case Style
DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- Current page: 147 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded
from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the
old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed
together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can
clear the interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition, and allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four
pins allow easy interface to a keypad and make it possible for wake-up on key-depression.
The interrupt on change feature is recommended for wake-up on key depression and operations
where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recom-
mended while using the interrupt on change feature.
Figure 9-5: Block Diagram of RB7:RB4 Pins
Any read or write of PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
Note 1: I/O pins have diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
3: In sleep mode the device is in Q1 state.
RB7:RB6 in serial programming mode
Data bus
WR TRIS
WR Port
RBPU
and clear the RBPU bit (OPTION<7>).
Set RBIF
From other
RB7:RB4 pins
(2)
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Section 9. I/O Ports
Q
Q
DD
Q
Q
Latch
and V
EN
EN
D
D
TTL
Input
Buffer
SS
.
V
P
DD
weak
pull-up
RD Port
Buffer
I/O
pin
Q1
DS31009A-page 9-7
Q3
(1)
ST
9
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