PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 205
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 205 of 414
- Download datasheet (4Mb)
16.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 16.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
never Idle
Name
EUSART Synchronous Slave
Reception
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
CSRC
SPEN
Bit 7
—
—
—
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
DTRXP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
PIC18F1XK50/PIC18LF1XK50
Preliminary
CKTXP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
ADDEN
SENDB
BRG16
16.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
RABIE
SSPIF
SSPIE
SSPIP
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
ABDEN
RABIF
RX9D
TX9D
DS41350C-page 203
Bit 0
on page
Values
Reset
279
282
282
282
281
281
281
281
281
281
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