PIC18F45J10-I/P Microchip Technology, PIC18F45J10-I/P Datasheet - Page 219
PIC18F45J10-I/P
Manufacturer Part Number
PIC18F45J10-I/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F45J10-I/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
MSSP/SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45J10-I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F45J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F45J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F45J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- PIC18F44J10-IPT PDF datasheet #7
- Current page: 219 of 358
- Download datasheet (6Mb)
17.7
Figure 17-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 17-5 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4
T
FIGURE 17-4:
FIGURE 17-5:
© 2007 Microchip Technology Inc.
AD
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
acquisition time before the conversion starts.
1
T
CY
Set GO/DONE bit
T
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
b8
1
3 T
AD
b9
2
b7
4 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
AD
b7
b5
4
6 T
T
AD
b4
5
b6
AD
7 T
PIC18F45J10 FAMILY
Cycles
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
AD
b3
b5
Note:
6
AD
8
wait is required before the next acquisition can
T
AD
b4
b2
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
8
b1
10
T
AD
b0
b2
ACQ
9
11
ACQ
= 0)
T
AD
10
= 4 T
Discharge
b1
1
AD
b0
DS39682C-page 217
11
)
T
Discharge
AD
1
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