PIC12C672-04/SM Microchip Technology, PIC12C672-04/SM Datasheet - Page 356
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PIC12C672-04/SM
Manufacturer Part Number
PIC12C672-04/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-04/SM
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C672-04/SM
Manufacturer:
MIC
Quantity:
141
Part Number:
PIC12C672-04/SM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 356 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
18.6.2
DS31018A-page 18-20
PIR
RCSTA
RCREG
PIE
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
Shaded cells are not used for Synchronous Slave Reception.
USART Synchronous Slave Reception
CSRC
SPEN
Bit 7
RX7
The operation of the synchronous master and slave modes is identical except in the case of the
SLEEP mode. Also, bit SREN is a don't care in slave mode.
If receive is enabled, by setting the CREN bit, prior to the SLEEP instruction, then a word may be
received during SLEEP. On completely receiving the word, the RSR register will transfer the data
to the RCREG register and if the RCIE enable bit bit is set, the interrupt generated will wake the
chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
Table 18-11: Registers Associated with Synchronous Slave Reception
Bit 6
RX9
RX6
TX9
Enable the synchronous master serial port by setting the SYNC and SPEN bits and clear-
ing the CSRC bit.
If interrupts are desired, then set the RCIE enable bit.
If 9-bit reception is desired, then set the RX9 bit.
To enable reception, set the CREN enable bit.
The RCIF bit will be set when reception is complete and an interrupt will be generated, if
the RCIE bit was set.
Read the RCSTA register to get the ninth bit (if enabled) and determine if any error
occurred during reception.
Read the 8-bit received data by reading the RCREG register.
If any error occurred, clear the error by clearing the CREN bit.
SREN CREN
TXEN SYNC
Bit 5
RX5
Bit 4
RX4
RCIF
RCIE
Bit 3
RX3
—
—
(1)
(1)
BRGH
FERR
Bit 2
RX2
OERR
TRMT
Bit 1
RX1
RX9D
TX9D
Bit 0
RX0
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
1997 Microchip Technology Inc.
POR,
BOR
0
0
other Resets
Value on all
0000 -00x
0000 0000
0000 -010
0000 0000
0
0
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