PIC18LF13K50-I/MQ Microchip Technology, PIC18LF13K50-I/MQ Datasheet - Page 23

• Manufacturer Part Number: PIC18LF13K50-I/MQ
• Description: IC PIC MCU FLASH 512KX8 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K50-I/MQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: PIC18
• No. Of I/o's: 15
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.0
5.1
Program Flash is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table
Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially
output on PGD.
TABLE 5-1:
FIGURE 5-1:
 2010 Microchip Technology Inc.
Step 1: Set Table Pointer
0000
0000
0000
0000
0000
0000
Step 2: Read memory and then shift out on PGD, LSb to MSb
1001
PGC
Command
PGD
Note 1:
4-bit
READING THE DEVICE
Read Program Flash, ID Locations
and Configuration Bits
Magnification of the high-impedance delay between PGC and PGD is shown in Figure 5-5.
1
1
READ PROGRAM FLASH SEQUENCE
2
0
0E <Addr[21:16]>
0E <Addr[15:8]>
0E <Addr[7:0]>
Data Payload
3
TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001)
0
4
6E F8
6E F7
6E F6
00 00
1
P5
PGD = Input
1
2
3
PIC18F1XK50/PIC18LF1XK50
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
Advance Information
5
6
7
8
P6
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low, as illustrated in Figure 5-1. This operation also
increments the Table Pointer by one, pointing to the
next byte in program Flash for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
9
LSb
P14
10
1
Core Instruction
11
2
PGD = Output
12
Shift Data Out
3
13
4
14
5
15
6
16
MSb
P5A
(Note 1)
Fetch Next 4-bit Command
1
PGD = Input
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DS41342E-page 23
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