AT89LP4052-20PU Atmel, AT89LP4052-20PU Datasheet - Page 52

• Manufacturer Part Number: AT89LP4052-20PU
• Description: IC 8051 MCU FLASH 4K 20DIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP4052-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 21-2.
Table 21-3.
22. Instruction Set Summary
52
WDTCON Address = A7H
Not Bit Addressable
Bit
Symbol
PS2
PS1
PS0
WDIDLE
WDTOVF
WDTEN
WDTCON Address = A6H
Not Bit Addressable
Bit
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading
the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to
WDTRST before the time-out interval expires.
AT89LP2052/LP4052
PS2
–
7
7
Function
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
Disable/enable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When
WDIDLE = 1, WDT freezes while the device is in IDLE mode.
Watchdog Overflow Flag. Set when a WDT reset is generated by the WDT timer overflow. Also set when an incorrect
sequence is written to WDTRST. Must be cleared by software.
Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The
WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST
WDTCON – Watchdog Control Register
WDTRST – Watchdog Reset Register
PS1
6
–
6
S
The AT89LP2052/LP4052 is fully binary compatible with the MCS-51 instruction set. The
difference between the AT89LP2052/LP4052 and the standard 8051 is the number of cycles
required to execute an instruction. Instructions in the AT89LP2052/LP4052 may take 1, 2, 3 or 4
clock cycles to complete. The execution times of most instructions may be computed using
Table
22-1.
PS0
–
5
5
WDIDLE
4
–
4
–
–
3
3
–
2
–
2
Reset Value = 0000 XX00B
WDTOVF
1
–
1
(Write-Only)
WDTEN
3547J–MICRO–10/09
–
0
0