PIC18F24J10-I/SP Microchip Technology, PIC18F24J10-I/SP Datasheet - Page 13
![IC PIC MCU FLASH 8KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F24J10-I/SP
Manufacturer Part Number
PIC18F24J10-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F24J10-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18F44J10-IPT PDF datasheet #6
- Current page: 13 of 358
- Download datasheet (6Mb)
FIGURE 1-2:
© 2007 Microchip Technology Inc.
Note 1:
V
OSC1
OSC2
T1OSI
T1OSO
MCLR
V
DDCORE
DD
Instruction Bus <16>
Table Pointer<21>
Program Memory
,
Address Latch
(16/32 Kbytes)
V
2:
Data Latch
inc/dec logic
SS
21
CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
BOR is not available in PIC18LF2XJ10/4XJ10 devices.
Comparator
BOR
Single-Supply
(2)
Programming
Debugger
Oscillator
Oscillator
20
8
In-Circuit
Internal
INTRC
Block
PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Decode and
Instruction
Table Latch
ROM Latch
Control
ECCP1
PCLATU
Timer0
PCU
Program Counter
IR
31 Level Stack
STKPTR
PCH
PCLATH
Start-up Timer
Clock Monitor
Brown-out
8
Watchdog
Power-up
Power-on
Oscillator
Fail-Safe
State Machine
Control Signals
Reset
Reset
PCL
Timer
Timer
Timer1
CCP2
Data Bus<8>
8
(2)
Timer2
Preliminary
MSSP
BITOP
BSR
Reference
Band Gap
Precision
4
3
8
Data Address<12>
Address
Decode
FSR0
FSR1
FSR2
inc/dec
Address Latch
logic
Data Memory
(3.9 Kbytes)
PRODH
Data Latch
8
ALU<8>
PIC18F45J10 FAMILY
EUSART
8 x 8 Multiply
12
10-bit
W
ADC
12
8
Access
8
Bank
PRODL
4
12
8
8
8
8
PORTB
PORTE
PORTA
PORTC
PORTD
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS1/C2OUT
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
RB4/KBI0/AN11
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
DS39682C-page 11
REF
REF
-/CV
+
(1)
(1)
REF
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