ATTINY25-20PU Atmel, ATTINY25-20PU Datasheet - Page 42

• Manufacturer Part Number: ATTINY25-20PU
• Description: IC AVR MCU 2K 20MHZ 8-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 4
• Height: 3.3 mm
• Length: 9.27 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.35 mm
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.1
8.2.2
42
ATtiny25/45/85
Power-on Reset
External Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 8-2.
Figure 8-3.
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer
than the minimum pulse width (see
ate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a
reset. When the applied signal reaches the Reset Threshold Voltage – V
edge, the delay counter starts the MCU after the Time-out period – t
CC
is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as
INTERNAL
INTERNAL
TIME-OUT
TIME-OUT
CC
RESET
RESET
RESET
RESET
V
V
decreases below the detection level.
CC
CC
“System and Reset Characteristics” on page
MCU Start-up, RESET Tied to V
MCU Start-up, RESET Extended Externally
V
V
V
POT
POT
RST
CC
t
TOUT
rise. The RESET signal is activated again, without any delay,
“System and Reset Characteristics” on page
CC
V
RST
t
TOUT
170. The POR is activated whenever
TOUT
– has expired.
RST
– on its positive
170) will gener-
2586M–AVR–07/10