PIC16F676-I/P Microchip Technology, PIC16F676-I/P Datasheet - Page 22

IC MCU FLASH 1K W/AD 14-DIP

PIC16F676-I/P

Manufacturer Part Number
PIC16F676-I/P
Description
IC MCU FLASH 1K W/AD 14-DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F676-I/P

Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
128 B
Height
3.3 mm
Length
19.05 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163029 - BOARD PICDEM FOR MECHATRONICSAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC16F630/676
REGISTER 3-2:
REGISTER 3-3:
3.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR'd together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
DS40039C-page 20
bit 7-6:
bit 5-0:
bit 7-6
bit 5-4
bit 3
bit 2-0
INTERRUPT-ON-CHANGE
TRISA — PORTA TRISTATE REGISTER (ADDRESS: 85h)
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
Unimplemented: Read as ’0’
TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
bit 7
Legend:
R = Readable bit
- n = Value at POR
Legend:
R = Readable bit
- n = Value at POR
Note:
U-0
U-0
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
TRISA<3> always reads 1.
U-0
U-0
TRISA5
WPUA5
R/W-x
R/W-1
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
TRISA4
WPUA4
R/W-x
R/W-1
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
Note:
Any read or write of PORTA. This will end the
mismatch condition.
Clear the flag bit RAIF.
TRISA3
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
R-1
WPUA2
R/W-1
TRISA2
R/W-x
 2003 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
R/W-1
TRISA1
R/W-x
WPUA0
TRISA0
R/W-1
R/W-x
bit 0
bit 0

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