PIC12CE518-04/SM Microchip Technology, PIC12CE518-04/SM Datasheet - Page 238

• Manufacturer Part Number: PIC12CE518-04/SM
• Description: IC MCU OTP 512X12 W/EE 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE518-04/SM

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 25Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
15.4.1
DS31015A-page 15-18
Slave Mode
In slave mode, the SCL and SDA pins must be configured as inputs (TRIS set). The SSP module
will override the input state with the output data when required (slave-transmitter).
When an address is matched or the data transfer after an address match is received, the hard-
ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-
ister with the received value currently in the SSPSR register.
There are certain conditions that will cause the SSP module not to give this ACK pulse. These
are if either (or both):
a)
b)
In this case, the SSPSR register value is not loaded into the SSPBUF, but the SSPIF and SSPOV
bits are set.
tus of bits BF and SSPOV. The shaded cells show the condition where user software did not prop-
erly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit
SSPOV is cleared through software.
The SCL clock input must have a minimum high and low time for proper operation. The high and
low times of the I
Device Data Sheet electrical specifications
The buffer full bit, BF (SSPSTAT<0>), was set before the message completed.
The overflow bit, SSPOV (SSPCON<6>), was set before the message completed.
Table 15-2
2
C specification as well as the requirement of the SSP module is shown in
shows what happens when a data transfer byte is received, given the sta-
parameters 100
and 101.
1997 Microchip Technology Inc.