PIC16F677-I/SO Microchip Technology, PIC16F677-I/SO Datasheet - Page 28
![IC PIC MCU FLASH 2KX14 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC16F677-I/SO
Manufacturer Part Number
PIC16F677-I/SO
Description
IC PIC MCU FLASH 2KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
5.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F677-I/SO
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
20-SOIC (7.5mm Width)
Mfg Application Notes
Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- PIC16F677-ISO PDF datasheet #5
- Current page: 28 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
2.2
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are located in the last 96 locations of each Bank.
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in each Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
RP1
2.2.1
The register file is organized as 128 x 8 in the
PIC16F687
PIC16F685/PIC16F689/PIC16F690. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Registers related to the operation of peripheral features
are described in the section of that peripheral feature.
DS41262E-page 26
0
0
1
1
RP0
0
1
0
1
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
→
→
→
→
and
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
256
x
8
in
the
© 2008 Microchip Technology Inc.
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