PIC12F635-I/SN Microchip Technology, PIC12F635-I/SN Datasheet - Page 128

• Manufacturer Part Number: PIC12F635-I/SN
• Description: IC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162057 - MPLAB ICD 2 HEADER 14DIP
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F635/PIC16F636/639
REGISTER 11-6:
REGISTER 11-7:
DS41232D-page 126
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
Note
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
AUTOCHSEL
COLPAR7
R/W-0
R/W-0
1:
Assured monotonic increment (or decrement) by design.
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
AUTOCHSEL: Auto Channel Select bit
1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of T
0 = Disabled – AFE follows channel enable/disable bits defined in Register 0
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mV
0 = Disabled – the AFE passes signal of any level it is capable of detecting
MODMIN<1:0>: Minimum Modulation Depth bit
00 = 50%
01 = 75%
10 = 25%
11 = 12%
LCZSEN<3:0>
0000 = -0dB (Default)
1111 = -30dB
R5PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
COLPAR6
R/W-0
AGCSIG
R/W-0
channel(s).
when the AGC begins regulating.
number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
an odd number of set bits.
odd number of set bits.
CONFIGURATION REGISTER 5
COLUMN PARITY REGISTER 6
:
W = Writable bit
‘1’ = Bit is set
(1)
W = Writable bit
‘1’ = Bit is set
COLPAR5
MODMIN1
: LCZ Sensitivity Reduction bit
R/W-0
R/W-0
COLPAR4
MODMIN0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLPAR3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
LCZSEN3
R/W-0
R/W-0
COLPAR2
LCZSEN2
R/W-0
R/W-0
PP
at input pins. The AGC Active Status bit is set
x = Bit is unknown
x = Bit is unknown
COLPAR1
LCZSEN1
R/W-0
R/W-0
© 2007 Microchip Technology Inc.
STAB
COLPAR0
LCZSEN0
; or otherwise, blocks the
R/W-0
R/W-0
R5PAR
R6PAR
R/W-0
R/W-0
bit 0
bit 0