GTL2003 Philips Semiconductors (Acquired by NXP), GTL2003 Datasheet

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GTL2003

Manufacturer Part Number
GTL2003
Description
Manufacturer
Philips Semiconductors (Acquired by NXP)
Datasheet

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1. General description
2. Features
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other eight matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
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GTL2003
8-bit bidirectional low voltage translator
Rev. 01 — 27 July 2007
8-bit bidirectional low voltage translator
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V
buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
Provides bidirectional voltage translation with no direction pin
Low 6.5
Supports hot insertion
No power supply required: will not latch up
5 V tolerant inputs
Low standby current
Flow-through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Packages offered: TSSOP20, DHVQFN20
ON-state resistance (R
on
) between input and output pins (Sn/Dn)
Product data sheet
CC
by

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GTL2003 Summary of contents

Page 1

... The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1 ...

Page 2

... TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm Ordering options Topside mark Temperature range 2003 +85 C GTL2003 +85 C DREF GREF SREF Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator 2 C-bus port translation to the 0.85 mm ...

Page 3

... Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator terminal 1 index area 2 SREF GTL2003BQ Transparent top view Fig 3. Pin configuration for DHVQFN20 Description ground (0 V) source of reference transistor Port S1 to Port S8 ...

Page 4

... V T Function selection, LOW-to-HIGH translation DREF SREF [ [ [ through an external resistor. CC Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator Input Dn Output [2][ [ Input Sn Output [2] [ ...

Page 5

... Typical bidirectional voltage translation. application Rev. 01 — 27 July 2007 8-bit bidirectional low voltage translator ). However, if either output 200 k GTL2002 GREF DREF D1 CHIPSET I/O D2 increase bit size by using 8-bit GTL2003, 10-bit GTL2010, or 22-bit GTL2000 D3 CHIPSET I GTL2003 1.5 V), the output 5 V totem pole or open-drain I 3.3 V ...

Page 6

... Typical unidirectional HIGH-to-LOW voltage translation. 1.8 V 1.5 V 1 CORE CPU I/O totem pole I/O or open-drain Typical unidirectional LOW-to-HIGH voltage translation. Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator through a pull-up resistor CC supply and SREF is set between 1 200 k GTL2002 GND GREF SREF DREF ...

Page 7

... V at stated current [1] Nominal + 10 % Nominal 465 512 1550 295 325 983 215 237 717 145 160 483 115 127 383 85 94 283 GTL2003 1705 1082 788 532 422 312 © NXP B.V. 2007. All rights reserved ...

Page 8

... Sn, Dn pin voltage on pin SREF voltage on pin DREF voltage on pin GREF pass switch current ambient temperature operating in free-air V 1.5 V for best results in level shifting applications. DREF Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator [1] Min [2] 0.5 [2] 0.5 [2] 0.5 [2] 0.5 [2] 0.5 < ...

Page 9

... GREF V = 1.5 V GREF mA GREF GREF GREF GREF = 25 C. amb Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator [1] Min Typ - 260 - - - - - 56 - 7.4 - 18.6 [2] - 3.5 - 4 [ ...

Page 10

... V M test jig output V HIGH-to-LOW LOW-to-HIGH DUT output HIGH-to-LOW LOW-to-HIGH GND to 3 Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator = 3 3 DD1 DD2 Figure 9. Min Typ [2][3] 0.5 1.5 [2][3] 0.5 1 1.5 V and T DD2 ...

Page 11

... PD PLH Rev. 01 — 27 July 2007 8-bit bidirectional low voltage translator = 50 pF; unless otherwise specified. L Min Typ [ 3 PHL V OH 1 002aab664 . PHL GTL2003 Max Unit 250 ps © NXP B.V. 2007. All rights reserved ...

Page 12

... V V DD2 DD2 150 k 150 k 150 DUT S1 S8 test jig 002aac643 open 500 GND 500 002aab667 Switch R L 500 open 500 7 V 500 open GTL2003 © NXP B.V. 2007. All rights reserved ...

Page 13

... Rev. 01 — 27 July 2007 8-bit bidirectional low voltage translator detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION GTL2003 SOT360 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...

Page 14

... JEDEC JEITA MO-241 - - - Rev. 01 — 27 July 2007 8-bit bidirectional low voltage translator detail 0.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION GTL2003 SOT764 ISSUE DATE 02-10-17 03-01-27 © NXP B.V. 2007. All rights reserved ...

Page 15

... Solder bath specifications, including temperature and impurities GTL2003_1 Product data sheet 8-bit bidirectional low voltage translator Rev. 01 — 27 July 2007 GTL2003 © NXP B.V. 2007. All rights reserved ...

Page 16

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 13. Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator Figure 13) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...

Page 17

... Inter-Integrated Circuit bus Low Voltage Transistor-Transistor Logic Machine Model Negative-channel Metal Oxide Semiconductor Transistor-Transistor Logic Transceiver Voltage Clamps Data sheet status Product data sheet Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator peak temperature 001aac844 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...

Page 18

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 27 July 2007 GTL2003 8-bit bidirectional low voltage translator © NXP B.V. 2007. All rights reserved ...

Page 19

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com GTL2003 All rights reserved. Date of release: 27 July 2007 Document identifier: GTL2003_1 ...

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