XE8000EV110 Semtech, XE8000EV110 Datasheet - Page 181

• Manufacturer Part Number: XE8000EV110
• Description: EVAL BOARD FOR XE8802AMI035LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV110

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC02MI035
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in
the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values.
In order to have glitch free outputs, the PWM outputs on PB(0) and PB(1) are sampled versions of these internal
PWM signals, therefore delayed by one counter clock cycle.
The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 20-14. Choosing a 16 bit PWM code which is higher than the maximum value
that can be represented by the number of bits chosen for the resolution results in a PWM output which is always
tied to 1.
The period of the PWM signal is given by the formula:
The duty cycle ratio DCR of the PWM signal is defined as:
DCR can be selected between
DCR in % in function of the RegCntX content(s) is given by the relation:
© Semtech 2006
Small PWM code
Large PWM code
Table 20-14: Resolution selection in cascaded PWM mode
2
PwmXsize(1:0)
resolution
100
DCR
11
10
01
00
Figure 20-3: PWM modulation examples
% and 100 %.
XE8802 Sensing Machine Data Acquisition MCU
=
MIN
Tper
DCR =
⎛
⎜
⎝
100
T
llarge
=
20-9
(
1
2
2
+
resolution
Tper
f
resolution
with ZoomingADC™ and LCD driver
Th
ckcnt
RegCntX
T
Resolution
lsmall
T
T
16 bits
14 bits
12 bits
10 bits
hlarge
per
)
,
100
⎞
⎟
⎠
T
hsmall
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