STEVAL-MKI109V1 STMicroelectronics, STEVAL-MKI109V1 Datasheet - Page 54

• Manufacturer Part Number: STEVAL-MKI109V1
• Description: MOTEHRBOARD MEMS ADAPTER STM32
• Manufacturer: STMicroelectronics
• Series: MEMSr

Specifications of STEVAL-MKI109V1

• Main Purpose: Motherboard; Accelerometer, Gyroscope
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: STM32 and MEMS Demo Boards
• Primary Attributes: DIL24 Socket for ST MEMS Adapter Boards
• Secondary Attributes: 3 V on-board linear voltage regulator
• Sensing Axis: Triple Axis
• Operating Voltage: 5 V
• Operating Current: 0.68 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LIS344ALH
• Other names: 497-10682

Electrical characteristics
54/69
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
DuCy(SCK)
t
t
t
t
t
t
dis(SO)
t
w(SCKH)
v(SO)
t
w(SCKL)
v(MO)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
h(NSS)
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
SCK
c(SCK)
(2)(3)
(2)(1)
(2)(1)
(2)
(2)(4)
(2)
(2)
(2)
(2)
(2)
(2)
Section 5.3.12: I/O port characteristics
(2)
(2)
(2)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time Slave mode, f
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
Table
Parameter
8.
Doc ID 15056 Rev 3
(1)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
PCLKx
Conditions
frequency and V
for more details on the input/output alternate
PCLK
PCLK
Table 40
= 20 MHz
= 36 MHz,
STM32F102x8, STM32F102xB
are derived from tests
DD
supply voltage conditions
4t
2t
Min
PCLK
PCLK
30
15
50
5
5
5
4
2
2
0
3t
Max
PCLK
18
10
25
70
60
18
5
8
MHz
Unit
ns
ns
%