ISL6740EVAL1 Intersil, ISL6740EVAL1 Datasheet - Page 23

• Manufacturer Part Number: ISL6740EVAL1
• Description: EVALUATION BOARD 1 ISL6740
• Manufacturer: Intersil

Specifications of ISL6740EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 12V
• Current - Output: 8A
• Voltage - Input: 48V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6740
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

A block diagram of the feedback control loop follows in
Figure 19.
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. A Type 3 error
amplifier configuration was selected.
The control to output transfer function may be represented
as [1]
where
Gain and phase plots of (Equation 26) appear below using
L = 4.0μH, C = 150μF, Rc = 28mΩ, Ro = 1.2Ω, and VIN = 75V.
v
----- -
v
o
c
Q
ω
ω
R
L = Output Inductance
C = Output Capacitance
R
V
=
o
z
S
o
c
----------------
V
=
=
= Output Capacitance ESR
V
=
= Output Load Resistance
= Sawtooth Ramp Amplitude
S
FIGURE 19. CONTROL LOOP BLOCK DIAGRAM
--------------- -
ω
IN
V
•
----------- -
-----------
R
o
R
ERR
2
LC
1
c
1
ISOLATION
•
o
FIGURE 20. TYPE 3 ERROR AMPLIFIER
C
•
L
N
------- -
N
S
P
PWM
•
------------------------------------------------ -
1
or
or
+
---------------- -
( )ω
Q
1
s
f
+
f
z
o
o
POWER
STAGE
------
ω
+
-
=
s
+
=
z
23
⎛
⎝
------------------ -
2πR
-------------------
2π LC
------ -
ω
REF
s
ERROR AMPLIFIER
o
1
⎞
⎠
1
2
c
C
Z
2
V
+
-
OUT
REF
Z
1
ISL6740, 1SL6741
(EQ. 26)
V
OUT
The Type 3 compensation configuration has three poles and
two zeros. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic for
the regulated output, the remaining poles and zeros for the
compensator are located at:
From (Equation 26), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitor and
inductor, and the output capacitance ESR. These variations
must be considered when compensating the control loop.
The worst case small signal operating point for a voltage
mode converter tends to be at maximum Vin, maximum load,
maximum C
f
f
f
f
p2
p3
z1
z2
-10
-20
-100
-150
-200
≈
≈
40
30
20
10
-50
=
=
50
0
------------------------------------- -
2π R4
---------------------------------------- -
2π R23
0
10
FIGURE 21B. CONTROL-TO-OUTPUT PHASE
---------------------------------------- -
2π R21
---------------------------------------- -
2π R21 C20
10
FIGURE 21A. CONTROL-TO-OUTPUT GAIN
•
•
•
•
OUT
1
1
1
1
•
, and minimum ESR.
•
100
C22
•
•
100
C22
C19
FREQUENCY (Hz)
1•10
FREQUENCY (Hz)
C19 C20
1•10
R23 R4
3
3
»
»
1•10
1•10
4
4
1•10
1•10
5
5
July 13, 2007
1•10
(EQ. 27)
(EQ. 28)
(EQ. 29)
(EQ. 30)
1•10
FN9111.4
6
6