MAX1282EVC16 Maxim Integrated Products, MAX1282EVC16 Datasheet - Page 15

• Manufacturer Part Number: MAX1282EVC16
• Description: EVAL KIT FOR MAX1282
• Manufacturer: Maxim Integrated Products

Specifications of MAX1282EVC16

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 400k
• Data Interface: Serial
• Inputs Per Adc: 4 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 13.75mW @ 400kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1282
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

progress and powers down into the specified low-qui-
escent-current state (2µA, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1282/MAX1283 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1,
a 0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corre-
sponding supply current and operating sections.
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. When returning to normal
operation—from SHDN, with an external reference—the
MAX1282/MAX1283 can be considered fully powered
up within 2µs of actively pulling SHDN high. When
using the internal reference, the conversion should be
initiated only when the reference has settled; its recov-
ery time is dependent on the external bypass capaci-
tors and the time between conversions.
The MAX1282/MAX1283 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 9 and 10 show the
average supply current as a function of the sampling
rate. The following sections discuss the various power-
down sequences. Other combinations of clock rates
Figure 5. Single-Conversion Timing
A/D STATE
SSTRB
SCLK
DOUT
DIN
CS
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
START
1
SEL
Power-Down Sequencing
2
SEL
1
IDLE
SEL
0
4
Hardware Power-Down
RB1
UNI/
BIP
(CLK = 6.4MHz)
SGL/
DIF PD2 PD2
400ns
t
ACQ
8
9
B11 B10 B9 B8 B7
12
RB2
and power-down modes may attain the lowest power
consumption in other applications.
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan-
nel per second. Figure 9a shows the MAX1283’s power
consumption for one- or four-channel conversions utiliz-
ing full power-down mode (PD1 = PD0 = 0), with the
internal reference and conversion controlled at the
maximum clock speed. A 0.01µF bypass capacitor at
REFADJ forms an RC filter with the internal 17kΩ refer-
ence resistor, with a 170µs time constant. To achieve
full 12-bit accuracy, nine time constants or 1.5ms are
required after power-up if the bypass capacitor is fully
discharged between conversions. Waiting this 1.5ms
duration in fast power-down (FASTPD) or reduced-
power (REDP) mode instead of in full power-up can fur-
ther reduce power consumption. This is achieved by
using the sequence shown in Figure 11a.
Figure 9b shows the MAX1283’s power consumption for
one- or four-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), with an external reference and
conversion controlled at the maximum clock speed.
One dummy conversion to power up the device is
needed, but no waiting time is necessary to start the
second conversion, thereby achieving lower power
consumption as low as half the full sampling rate.
CONVERSION
16
B6
B5 B4 B3 B2 B1 B0
Using Full Power-Down Mode
20
RB3
IDLE
24
15