MAX115EVB16 Maxim Integrated Products, MAX115EVB16 Datasheet - Page 9

• Manufacturer Part Number: MAX115EVB16
• Description: EVAL KIT FOR MAX115
• Manufacturer: Maxim Integrated Products

Specifications of MAX115EVB16

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 116k
• Data Interface: Parallel
• Inputs Per Adc: 8 Single Ended
• Input Range: ±5 V
• Power (typ) @ Conditions: 17mW @ 116kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX115
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX115/MAX116 feature four simultaneous T/Hs.
Each T/H has two multiplexed inputs. A T-switch input
configuration provides excellent hold-mode isolation.
Allow 600ns acquisition time for 12-bit accuracy.
The T/H aperture delay is typically 10ns. The 500ps
aperture-delay mismatch between the T/Hs allows the
relative phase information of up to four different inputs
to be preserved. Figure 3 shows the equivalent input
circuit, illustrating the ADC’s sampling architecture.
Only one of four T/H stages with its two multiplexed
inputs (CH_A and CH_B) is shown. All switches are in
track configuration for channel A. An internal buffer
charges the hold capacitor to minimize the required
Figure 4. Timing Diagram
Figure 5. Programming a Four-Channel Conversion, Input Mux A
CONVST
DATA
INT
WR
CS
RD
(LSB)
WR
CS
t
A0
A1
A2
A3
AS
t
CWS
t
DATA IN
WR
_______________________________________________________________________________________
t
CWH
t
2x4-Channel, Simultaneous-Sampling
AH
t
CW
t
Track/Holds
CONV
t
CRS
t
DA
t
ID
t
RD
CH1
t
RD
t
acquisition time between conversions. The analog input
appears as a 10kΩ resistor in parallel with a 16pF
capacitor for the MAX115 and as a 1MΩ resistor in par-
allel with a 16pF capacitor for the MAX116.
Between conversions, the buffer input is connected to
channel 1 of the selected track/hold bank. When a
channel is not selected, switches S1, S2, and S3 are
placed in hold mode to improve channel-to-channel
isolation.
Input data (A0–A3) and output data (D0–D11) are multi-
plexed on a three-state bidirectional interface. This par-
allel I/O can easily be interfaced with a microprocessor
(µP) or DSP. CS, WR, and RD control the write and read
operations. CS is the standard chip-select signal, which
enables the controller to address the MAX115/MAX116
as an I/O port. When CS is high, it disables the WR and
RD inputs and forces the interface into a high-Z state.
Figure 4 details the interface timing.
The MAX115/MAX116 have eight conversion modes
plus power-down, which are programmed through a
bidirectional parallel interface. At power-up, the devices
default to the Input Mux A/Single-Channel Conversion
mode. The user can select between two banks (mux
inputs A or mux inputs B) of four simultaneous-sampled
input channels, as illustrated in Figure 2. An internal
microsequencer can be programmed to convert one to
four channels of the selected bank per sample. For a
single-channel conversion, CH1 is digitized, and then
INT goes low to indicate completion of the conversion.
DH
t
CRH
CH2
t
ACQ
CH3
12-Bit ADCs
CH4
Programming Modes
Digital Interface
9