MAX1448EVKIT Maxim Integrated Products, MAX1448EVKIT Datasheet - Page 11

• Manufacturer Part Number: MAX1448EVKIT
• Description: EVAL KIT FOR MAX1448
• Manufacturer: Maxim Integrated Products

Specifications of MAX1448EVKIT

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±1 V
• Power (typ) @ Conditions: 120mW @ 80MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1448
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1448 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half clock-cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated. Each stage provides a 1-bit reso-
lution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through S4a and S4b. S2a and S2b set the
common mode for the amplifier input and open simulta-
Figure 1. Pipelined Architecture—Stage Blocks
_______________Detailed Description
V
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
IN
V
IN
= INPUT VOLTAGE BETWEEN
V
IN
FLASH
ADC
1.5 BITS
STAGE 1
T/H
______________________________________________________________________________________
Input Track-and-Hold Circuit
10-Bit, 80Msps, Single 3.0V, Low-Power
DAC
MDAC
DIGITAL CORRECTION LOGIC
Σ
STAGE 2
D9–D0
10
x2
V
OUT
STAGE 10
ADC with Internal Reference
neously with S1, sampling the input waveform. S4a and
S4b are then opened before S3a and S3b connect
capacitors C1a and C1b to the amplifier output, and
S4c is closed. The resulting differential voltage is held
on C2a and C2b. The amplifier is used to charge C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-chang-
ing input. The wide-input-bandwidth T/H amplifier
allows the MAX1448 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. Analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (V
The MAX1448 full-scale range is determined by the
internally generated voltage difference between REFP
(V
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (V
are internally buffered, low-impedance outputs.
Figure 2. Internal Track-and-Hold Circuit
Analog Input and Reference Configuration
DD
IN+
IN-
/2 + V
TRACK
S4a
S4b
REFIN
HOLD
TRACK
/4) and REFN (V
S4c
HOLD
C2a
C2b
DD
CLK
INTERNAL
S2a
INTERNAL
/2) for optimum performance.
INTERNAL
NON OVERLAPPING
CLOCK SIGNALS
BIAS
BIAS
S1
S2b
DD
/2 - V
C1a
C1b
DD
COM
COM
/2), and REFN
REFIN
S5a
S5b
S3a
S3b
/4). The
OUT
OUT
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