HI7190EVAL Intersil, HI7190EVAL Datasheet - Page 18

• Manufacturer Part Number: HI7190EVAL
• Description: EVALUATION PLATFORM HI7190
• Manufacturer: Intersil

Specifications of HI7190EVAL

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 15mW @ 200kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI7190
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Instruction Register
The Instruction Register is an 8-bit register which is used
during a communications cycle for setting up read/write
operations.
R/W - Bit 7 of the Instruction Register determines whether a
read or write operation will be done following the instruction
byte load. 0 = READ, 1 = WRITE.
MB1, MB0 - Bits 6 and 5 of the Instruction Register
determine the number of bytes that will be accessed
following the instruction byte load. See Table 5 for the
number of bytes to transfer in the transfer cycle.
FSC - Bit 4 is used to determine whether a Positive Full Scale
Calibration Register I/O transfer (FSC = 0) or a Negative Full
Scale Calibration Register I/O transfer (FSC = 1) is being
performed (see Table 6).
A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction
Register determine which internal register will be accessed
while bits 1 and 0 (A1 and A0) determine which byte of that
register will be accessed first. See Table 6 for the address
decode.
FSC A3 A2 A1 A0
MSB
R/W
X
X
X
X
X
X
X
X
X
0
0
0
TABLE 6. INTERNAL DATA ACCESS DECODE STARTING
MB1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
MB1
TABLE 5. MULTIPLE BYTE ACCESS BITS
6
0
0
0
1
1
1
0
0
0
1
1
1
BYTE
MB0
0
0
1
0
0
1
0
0
1
0
0
1
MB0
0
1
0
1
INSTRUCTION REGISTER
5
0
1
0
0
1
0
0
1
0
0
1
0
Data Output Register, Byte 0
Data Output Register, Byte 1
Data Output Register, Byte 2
Control Register, Byte 0
Control Register, Byte 1
Control Register, Byte 2
Offset Cal Register, Byte 0
Offset Cal Register, Byte 1
Offset Cal Register, Byte 2
Positive Full Scale Cal Register, Byte 0
Positive Full Scale Cal Register, Byte 1
Positive Full Scale Cal Register, Byte 2
FSC
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
4
18
A3
3
DESCRIPTION
DESCRIPTION
A2
2
A1
1
LSB
A0
HI7190
Write Operation
Data can be written to the Control Register, Offset
Calibration Register, Positive Full Scale Calibration Register,
and the Negative Full Scale Calibration Register. Write
operations are done using the SDIO, CS and SCLK lines
only, as all data is written into the HI7190 via the SDIO line
even when using the 3-wire configuration. Figures 14 and 15
show typical write timing diagrams.
The communication cycle is started by asserting the CS line
low and starting the clock from its idle state. To assert a write
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a write transfer
(R/W = 1).
When writing to the serial port, data is latched into the
HI7190 on the rising edge of SCLK. Data can then be
changed on the falling edge of SCLK. Data can also be
changed on the rising edge of SCLK due to the 0ns hold time
required on the data. This is useful in pipelined applications
where the data is latched on the rising edge of the clock.
Read Operation - 3-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale
Calibration Register, and the Negative Full Scale Calibration
Register. When configured in 3-wire transfer mode, read
operations are done using the SDIO, SDO, CS and SCLK
lines. All data is read via the SDO line. Figures 16 and 17
show typical 3-wire read timing diagrams.
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a read transfer
(R/W = 0).
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Read Operation - 2-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale
Calibration Register, and the Negative Full Scale Calibration
Register. When configured in two-wire transfer mode, read
operations are done using the SDIO, CS and SCLK lines. All
data is read via the SDIO line. Figures 18 and 19 show
typical 2-wire read timing diagrams.
FSC A3 A2 A1 A0
1
1
1
TABLE 6. INTERNAL DATA ACCESS DECODE STARTING
1
1
1
1
1
1
BYTE (Continued)
0
0
1
0
1
0
Negative Full Scale Cal Register, Byte 0
Negative Full Scale Cal Register, Byte 1
Negative Full Scale Cal Register, Byte 2
DESCRIPTION
June 27, 2006
FN3612.10