HI7190EVAL Intersil, HI7190EVAL Datasheet - Page 15

• Manufacturer Part Number: HI7190EVAL
• Description: EVALUATION PLATFORM HI7190
• Manufacturer: Intersil

Specifications of HI7190EVAL

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 15mW @ 200kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI7190
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

System Offset/Internal Gain Calibration Mode
Please note: System Offset/Internal Gain is only valid when
operating in a gain of one. In addition, the offset and gain errors
are not reduced as with the full system calibration.
The System Offset/Internal Gain Calibration Mode is a single
step process that updates the Offset Calibration Register,
the Positive Full Scale Calibration Register, and the
Negative Full Scale Calibration Register. First the external
differential signal applied to the V
that value is stored in the Offset Calibration Register. The
user must apply the zero point or offset voltage to the
HI7190 analog inputs and allow the signal to settle before
selecting this mode.
After this is completed the Positive and Negative Full Scale
Calibration Registers are updated. The inputs V
are disconnected and the external reference is switched in. The
HI7190 then takes 3 conversion cycles to sample the data and
update the Positive Full Scale Calibration Register. Next the
polarity of the reference voltage across the V
terminals is reversed and after 3 conversion cycles the
Negative Full Calibration Register is updated. The values
stored in the Positive and Negative Full Scale Calibration
Registers correct for any internal gain errors in the A/D transfer
function. After 3 more conversion cycles, the DRDY line will
activate signaling that the calibration is complete and valid data
is present in the Data Output Register.
System Gain Calibration Mode
The Gain Calibration Mode is a single step process that
updates the Positive and Negative Full Scale Calibration
Registers. This mode will convert the external differential
signal applied to the V
the Negative Full Scale Calibration Register. Then the
polarity of the input is reversed internally and another
conversion is performed. This conversion result is written to
the Positive Full Scale Calibration Register. The user must
apply the +Full Scale voltage to the HI7190 analog inputs
and allow the signal to settle before selecting this mode.
After 1 more conversion period the DRDY line will activate
signaling the calibration is complete and valid data is present
in the data output register.
Reserved
This mode is not used in the HI7190 and should not be
selected. There is no internal detection logic to keep this
condition from being selected and care should be taken not
to assert this bit combination.
Offset and Span Limits
There are limits to the amount of offset and gain which can
be adjusted out for the HI7190. For both bipolar and unipolar
modes the minimum and maximum input spans are
0.2 x V
In the unipolar mode the offset plus the span cannot exceed
the 1.2 x V
REF
REF
/GAIN and 1.2 x V
/GAIN limit. So, if the span is at its minimum
IN
inputs and then store that value in
15
REF
IN
/GAIN respectively.
inputs is converted and
INHI
INHI
and V
and V
INLO
INLO
HI7190
value of 0.2 x V
V
the voltage used for the zero scale point. For this mode the
offset plus half the span cannot exceed 1.2 x V
the span is at ±0.2 x V
greater than ±2 x V
Serial Interface
The HI7190 has a flexible, synchronous serial communication
port to allow easy interfacing to many industry standard
microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including
both the Motorola 6805/11 SPI and Intel 8051 SSR protocols.
The Serial Interface is a flexible 2-wire or 3-wire hardware
interface where the HI7190 can be configured to read and
write on a single bidirectional line (SDIO) or configured for
writing on SDIO and reading on the SDO line.
The interface is byte organized with each register byte
having a specific address and single or multiple byte
transfers are supported. In addition, the interface allows
flexibility as to the byte and bit access order. That is, the user
can specify MSB/LSB first bit positioning and can access
bytes in ascending/descending order from any byte position.
The serial interface allows the user to communicate with 5
registers that control the operation of the device.
Data Output Register - a 24-bit, read only register
containing the conversion results.
Control Register - a 24-bit, read/write register containing
the setup and operating modes of the device.
Offset Calibration Register - a 24-bit, read/write register
used for calibrating the zero point of the converter or system.
Positive Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Positive Full Scale
point of the converter or system.
Negative Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Negative Full
Scale point of the converter or system.
Two clock modes are supported. The HI7190 can accept the
serial interface clock (SCLK) as an input from the system or
generate the SCLK signal as an output. If the MODE pin is
logic low the HI7190 is in external clocking mode and the
SCLK pin is configured as an input. In this mode the user
supplies the serial interface clock and all interface timing
specifications are synchronous to this input. If the MODE pin
is logic high the HI7190 is in self-clocking mode and the
SCLK pin is configured as an output. In self-clocking mode,
SCLK runs at F
boundaries. SCLK does NOT have the capability to stall low
in this mode. All interface timing specifications are
synchronous to the SCLK output.
Normal operation in self-clocking mode is as follows (See
Figure 12): CS is sampled low on falling OSC
REF
/GAIN. In bipolar mode the span is equidistant around
SCLK
REF
REF
/GAIN, the offset must be less than 1 x
= OSC
REF
/GAIN.
/GAIN, then the offset can not be
1
/8 and stalls high at byte
1
REF
edges. The
June 27, 2006
/GAIN. If
FN3612.10