CDB5530U Cirrus Logic Inc, CDB5530U Datasheet - Page 11

• Manufacturer Part Number: CDB5530U
• Description: BOARD EVAL FOR CS5530
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5530U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5530
• Product: Data Conversion Development Tools
• Resolution: 24 bit
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5530
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1158

2. GENERAL DESCRIPTION
The CS5530 is a ΔΣ Analog-to-Digital Converter
(ADC) which uses charge-balance techniques to
achieve 24-bit performance. The ADC is optimized
for measuring low-level unipolar or bipolar signals
in weigh scale, process control, scientific, and med-
ical applications.
To accommodate these applications, the ADC in-
cludes a very-low-noise, chopper-stabilized instru-
mentation amplifier (12 nV/√Hz @ 0.1 Hz) with a
gain of 64X. This ADC also includes a fourth-order
ΔΣ modulator followed by a digital filter which pro-
vides twenty selectable output word rates of 6.25,
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 samples
per second (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi-
crowire compatible with a Schmitt-trigger input on
the serial clock (SCLK).
2.1 Analog Input
Figure 3 illustrates a block diagram of the CS5530.
The front end includes a chopper-stabilized instru-
mentation amplifier with a gain of 64X.
DS742F3
AIN+
AIN-
64x
1000
1000 Ω
22 nF
Ω
C1 PIN
C2 PIN
Figure 3. Front End Configuration
VREF+
X1
Differential
Modulator
4
th
ΔΣ
Order
VREF-
X1
The amplifier is chopper-stabilized and operates with
a chop clock frequency of MCLK/128. The CVF
(sampling) current into the instrumentation amplifier
is typically 1200 pA over
(MCLK=4.9152 MHz). The common-mode plus sig-
nal range of the instrumentation amplifier is (VA-) +
1.6 V to (VA+) - 1.6 V.
Figure 4 illustrates the input model for the 64X am-
plifier.
Note:
V
i = fV
n
os
Digital
≤ 8 mV
Figure 4. Input Model for AIN+ and AIN- Pins
Filter
Sinc
AIN
os
The C = 3.9 pF capacitor is for input current
modeling only. For physical input capacitance
see ‘Input Capacitance’ specification under
Analog Characteristics.
C
5
Programmable
f =
Digital Filter
MCLK
Sinc
128
3
C = 3 .9 pF
-40°C to +85°C
CS5530
Serial
Port
11